verification 2+

RESUME

MAHESH KUMAR

#***, *** ****, ******** *****, E-mail:*************@*****.*** . IAF post, yelahanka, Phone : 098***-*****

Bangalore, Karnataka, India-560063.

Career Objective

To have a challenging and growth oriented career in the field of VLSI IC design.

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Experience Summary :

2+ years of experience in VLSI Design and Verification using Verilog, SystemVerilog and Teaching.

Currently working as a Lecturer in KNS Institute of Technology, Bangalore.

Professional Work Experience :

Current : KNSIT, Bangalore

Duration: Feb 2009 to till date.

Position : Lecturer.

Previous : Nuntius Systems (India) Pvt.Ltd.

Duration : Jan 2007 to Feb-2009

Position : Member Technical Staff – VLSI Design Group.

Educational qualification:

2006-2008, Master of Science (MS) in VLSI CAD from Manipal Centre for Information Science (MCIS), a Constitute institute of MANIPAL UNIVERSITY, with a CGPA of 8.32 / 10.

2001-2005, Bachelor of Engineering, Electronics and communication (B.E) passed out with an aggregate of 65.98% form KNS Institute of Technology of Visweshwaraiah Technological University, Karnataka.

1999-2001, Pre-University College from board of PU, passed out with an aggregate of 63.50% from Seshadripuram Composite PU College, Bangalore.

Professional skills :

Hardware Skills : Logic Design and HDL, ASIC, Front End/FPGA.

EDA Tools : Cadence-NCsim, Xilinx ISE 9.1i , Model sim 6.0, QuestaSim.

Hardware Description Languages: Verilog HDL, VHDL

Hardware Verification Languages: System Verilog.

Programming Skills : C, C++.

Scripting Language : Basics of TCL.

Methodologies : OVM.

Bus Protocols : Mil-Std-1553, Arinc-429, I2C, SPI.

Projects Handled :

Project #1

Title : DEVELOPMENT OF OPEN VERIFICATION IP FOR I2C CONTROLLER.

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of

data exchange between devices. It is most suitable for applications requiring occasional

communication over a short distance between many devices. The I2C standard is a true

multi-master bus including collision detection and arbitration that prevents data

corruption if two or more masters attempt to control the bus simultaneously.

Environment :System Verilog

Tools : Cadence-NCsim, Sim-Vision.

Team size : 2

Project #2

Title : SERIAL PERIPHERIAL INTERFACE.

The SPI core has five 32-bit registers. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. All transfers are full duplex transfers of a programmable number of bits per transfer (up to 64 bits).

Full duplex synchronous serial data transfer.

Variable length of transfer word up to 128 bits.

MSB or LSB first data transfer.

Rx and Tx on both rising or falling edge of serial clock independently.

The project is coded in Verilog HDL, it is simulated Cadence-NCsim.

Environment : Verilog

Tools : Cadence-NCsim

Team size : 2

Project #3

Title : SPARTAN-3E FPGA BASED MIL-STD-1553 AND ARINC PROTOCOL (AVEIONICS BUS).

Description: MIL-STD-1553 is military standard published by the United States Department of Defense

The mechanical, electrical and functional characteristics of a serial data bus. It was originally designed for use with military avionics, but has also become commonly used in spacecraft on-board data handling (OBDH) subsystems, both military and civil.

Responsibilities:

Responsible in developing Verification Environment.

Environment: VHDL

Tools: Xilinx ISE 9.1i

Team size – 2

Hobbies and Interests :

Surfing, Playing & Watching Cricket, Collecting Stamps & coins

Strengths :

Good interpersonal communication skills.

Analytical ability, critical thinking and problem solving.

Positive attitude, Work orientation and professionalism.

Able to handle multiple tasks simultaneously, and work effectively in a team or individual.

Personal Details :

Mother’s Name : Ratnamma.

Father’s Name : Kondaiah.

Date of Birth : 10 December 1983

Sex : Male.

Passport Number : F5108210

Languages Known : English, Hindi, Kannada, Telugu and Tamil.

Nationality : Indian.

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Bangalore (Mahesh Kumar).

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