Neelima Namburi Email: l6qx6r@r.postjobfree.com

**** *********** *****, ***# **, Pittsburgh, PA- 15220 Cell: 412-***-****

Objective: Seeking a co-op or full time position as Electrical Project/Product Engineer.

Education:

Master of Science, Electrical & Electronics Engineering, University of Hartford• GPA 3.68• (Jan 2008-May 2010)

Bachelors of Engineering, Electronics and Communication Engineering, Anna University, India •GPA 3.98• (May 2003-May2007)

Computer Skills:

Programming: Ms-project, Verilog, System Verilog, VHDL, C, C++, Perl Scripting, C#, Assembly Language (x85, x86, x51)

Software/Tools: Synopsys, VCS simulator, Prime time, Design Vision, Multisim, L-EDIT, Cadence, Orcad, Xilinx ISE, Modelsim , TimeQuest Timing Analyzer, ADS, Matlab, SUMULINK, Pspice, Design Compiler, LVS, LABVIEW 8.6, SPSS

Hardware: FPGA, DSP, Digital & Analog Design, CMOS ASIC, DFT, CAD, Auto CAD, ATPG, STA

Bus Protocols: CPU, USB, PCI, PCI express, TCP/IP, GUI, BIOS

Operating Systems:MS Windows 95/98/XP/Vista, UNIX

Skills:

1. Excellent in troubleshooting problems and finding solutions

2. Expert on a range of hardware and software applications used.

3. PCB designing and layout.

4. Analog and Digital circuits design and testing.

5. CAD, LabView and MatLab designing for testing and simulation.

6. I take the overall responsibility for the successful planning, decision making, execution, monitoring, control and closure of a project.

7. I advise innovative features to be added to products for betterment of the product as a part of Product development.

Projects:

Managed six projects simultaneously for OTIS implementations. The basic plan was to track the tasks and assign resources. Follow-up with the resources on a daily basis and conduct meetings to get the things completed according to the time lines created.

Managed various implementations and Enhancement projects for Mobile Aspects with health care professionals.

Managed System Design Project: Designed a Portable Beverage Cooling and Heating Device that use Thermoelectric Modules to control the temperature of the Beverage. University of Hartford.

Environment: PSPICE, LABVIEW

Managed projects in Power Electronics: DC-DC converters (Boost,Buck and Buck-boost converters),Designed the PCB’s for these converters and simulated in LabView. University of Hartford.

Managed DSP projects on Speech Processing, Noise Filtering, Echo Cancellation using Mat lab. OTIS(June 2009-April 2010)

CMOS and VLSI using SRAM, FLASH, ADC, LCD Display, Xilinx, Logic Works, PSPICE, L-Edit:

Designed interface logic between SRAM and FLASH, SRAM and ADC. Address and Data Bus were displayed on 7 Segment LCD Display, implemented in Xilinx FPGA XCV2000, verified using logic analyzer, VHDL and Verilog.

Designed and produced Layout of the Bubble Suppress and Decode logic circuit for a 3 Bit Flash ADC. The design of the circuit included transistor sizing, load calculations and optimized layout was made in L-Edit Integrated Circuit Layout Editor.

PCI, Cache and Parallel Computer Architectures using Xilinx:

As a member of three person team, designed a two way set associative cache controller, which has 8KB cache memory, 32KB main memory and 4GB virtual memory using VCS. Multiprocessor & Multi cache MESI protocol is also included in design. Main memory is also designed. The controller has snooping capability and cache coherency is done through write back method.

Designed PCI Device with one target and initiator to do write cycle, implemented in Verilog and simulated on Synopsis VCS tool.

Designed Cache and Virtual memory supporting Cache Hit, Cache Miss, and Page Fault. The design was implemented in Verilog.

Advanced VLSI Design using LEDIT, PSPICE, CAD:

Submitted a research paper on DDR3 SDRAM (Double Data Rate Three Synchronous Dynamic Random Access Memory).

Specialties/Relevant Course:

Advanced Logic Design and Hierarchical Design Methodology:

In depth knowledge of design of combinational circuits, latches, flip-flops, clocked sequential circuits, synchronous and asynchronous finite state machines.

Strong background in the (FPGA) behavioral/RTL design (VERILOG/VHDL), simulation, functional, formal verification, testing, debugging and synthesis, design rule checking, LVS tools, setup/hold time constraints, meta stability and clocking Hazards

Commercial EDA tool sets used to synthesize lab projects containing a hierarchy of modules into FPGAs. Post synthesis

simulations by these same tools verify the design before implementation on rapid prototyping boards in the lab.

Knowledge of ASIC design and verification: static timing analysis, floor planning, CTS, placement, routing, DFM, critical path analysis and hands on Synopsis tools design compiler, design vision, prime time and scripting language TCL, C and Perl.

CMOS and VLSI Design:

In-depth experience and good understanding of very large-scale integration (VLSI) complementary metal-oxide semiconductor (CMOS) logic Designs, semiconductor device physics and semiconductor manufacturing and power issues in CMOS circuits

Strong background in CMOS logic styles - static, dynamic, complimentary logic, pass transistor logic, rationed logic, etc.

Substantial experience in analog/mixed-signal IC, knowledgeable in CMOS VLSI design and Graphical User Interface.

Working knowledge and good understanding on architecture, testing and processing flow of semiconductors memories (SRAM, DRAM, ROM, NAND flash and NOR flash)

Hands-on experience in handling different EDA tools like cadence, SPICE, Synopsys, Design Vision/Analyzer, simulation of basic VLSI layouts using LEDIT, floor planning, placement, routing, CTS, Physical and formal verification.

VLSI Testing and Design-For-Test applications:

Substantial knowledge of IC manufacturing flow, E-test, assembly, wafer sort test, Burn In, Class test, point defects, parametric defects, fabrication, yield, design for test, Quality and Reliability & fault grade.

In depth experience in design for testability, IDDq test, built-in self test, non-exhaustive testing, CMOS parametric & performance, production test, Schmoo plot, functional/ At speed testing, DC parametric specs testing.

Knowledge in memory-specific test methodology and special features of memory designs employed in high volume manufacturing for improved testability, yield, reliability, ASIC system on chip VLSI design and failure modes, detection and prevention.

Proficient in Fault Modeling and Simulation Techniques, DFT Techniques, structural scan test and ATPG, Path Delay Testing, Boundary Scan, BIST, IDDQ Test and SoC Test architecture.

Micro-Computer System Design:

Knowledge of Design of the microprocessor based computer system and pipe ling.

In depth knowledge of ISA, PCI and PCI Express bus architecture, bus arbitration, system architecture, timing, BIOS specification and also have good platform debugging skills.

Working knowledge of cache architecture, PCI, virtual memory, paging, segmentation, MESI protocol, graphical user interface, multi threaded, superscalar processors and interrupt schemes

Working knowledge of uni and multi processor systems, pipeline and array processors, and parallel memory organizations.

Related Work Experience:

1.Worked as DSP Engineer(Aug 2008- Aug 2010), OTIS elevators, CT

2.Worked as a Electronic Technician in University of Hartford University of Hartford.

3.Currently, working as Project and Implementations Engineer (Aug 2010- present) in the field of testing, implementations and project planning

Mobile Aspects, Pittsburgh.

4.Worked as Graduate Assistant (Dec 2007 – Aug 2008) in Electrical Engineering Dept, UHART

5.Worked as Teaching Assistant (Aug 2008 – Dec 2010) in Electrical Engineering Dept, UHART

6.Worked as Electronic technician and Electronics Lab Assistant (Dec 2009- Aug 2010), Connecticut Center of Advanced Technology

Achievements:

I was awarded graduate and teaching assistant ships throughout my Graduate studies.

My research paper was published on International Journal of Industrial Engineering and Production Research, IJIEPR.

References:

Furnished upon Request

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