Sr. Technical Staff Director & Program Manager

Jeffrey C. Smith (Resume)

Sr. Technical Staff and Development Director

***** ********** ***** **. 480-***-****

Home

Scottsdale Az 85258 408-***-****

Mobile

E-mail: ************@*****.***

Primary Skills

Startup, emerging growth, small business, and large corporate experiences. Strong project management expertise.

Proficient in all Phases of Engineering Projects – Design, Test, System Integration, Support, Documentation, Project

and

Design Review, Future Product Architecture and Development, Market and Competitor Analysis, Sales and Marketing,

Customer Development and Support, Training and Leadership.

Highly Motivated, Business Minded, and a High Level of Commitment and Perspective. Managed many products

from start

to a profitable finish in a timely and cost effective manner.

SUMMARY OF QUALIFICATIONS

• High energy engineering and management professional, with proven multidisciplinary technical and leadership skills.

• Successful 24 year career demonstrating high achievement at all levels of engineering and management.

• Proven track record taking product from concept to production. Planning and executing all phases.

• Excellent leadership and interpersonal skills, fostering teamwork, loyalty and productivity.

• Able to motivate team and produce high quality and high volume systems and products within schedule and budget.

• Ability to evaluate market trends and to make sound judgments on development processes and future product

directions.

• Experienced in providing the face of engineering to customers, demonstrating and selling the technology/product and

a

keen sense for business and integrating engineering with organizational goals.

• Significant international experience and proven ability to manage dispersed engineering teams and international

partners.

Work Experience

Sr. Technical Staff & Development Director

Internet Connectivity Group (ICG) Lake Forest, CA; 2008 to Present

* Responsible for the implementation and release of all hardware products, including electrical and mechanical design,

test and certification, documentation and manufacturing release.

* Able to multi task: developed and supported release of products simultaneously.

* Improved and refined engineering development and release processes. Adopted and implemented board diagnostic

strategies to support board development, validation, manufacturing, and test processes.

* Developed next generation wireless internet digital signage system hardware processing and IO video, wireless

802.11 G (for WiFi) and 802.11 N Receivers and transmitters (for video), and 3/4G Router cards.

* Developed next generation digital edge QAM device supporting 54MHz 1GHz output bandwidth The product is a

modular design and converts MPEG 2 over IP into 128 QAM outputs.

* Drove critical ASIC and component selection processes, including the selection of the AD video trans coder chips, the

FPGAs, and the PPC CPU. This high density board trans coded MPEG 2 streams. Developed NIC boards with PCIe

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Jeffrey C. Smith (Resume)

Sr. Technical Staff and Development Director

10110 Doubletree Ranch Rd. 480-***-****

Home

Scottsdale Az 85258 408-***-****

Mobile

E-mail: ************@*****.***

implementing Ralink's processor chips, flash CPU sub system, Xilinx LX40 FPGA, and multiple interfaces and DDR2

devices.

* Developed leading edge MPEG 2 to digital edge QAM line card supporting direct digital synthesis for up to 160

simultaneous QAMs on a single RF channel and multiple RF channels per board. Architecture and critical component

selection for flexible modular designs for future products platforms, upgrades, and video processing. Utilized PCIe and

1GE as transport pipes (SerDes), high performance DSP centric FPGAs, and multi core CPUs to support high

throughput data and processing requirements.

* Developed multiple chassis and platforms Optimized board placement within chassis to achieve thermal and

electrical performance requirements. Managed Certification EMC, Compliance, Safety, and Evaluated and selected

contract manufacturing.

* Formed and created strong vendor relationships with component vendors including Xilinx, RaLink, Molex, Tyco,

Pulse, Analog Devices, ASUS, and others, tool vendors, mechanical tooling and manufacturing vendors, rework houses,

engineering design and test service organizations, component distributors, and PCB design houses.

* Developed outsourcing strategy and outsourced several products. Managed Sub contract Engineers and designs.

* Negotiated extremely favorable pricing on all product development aspects including components, tools, test

equipment to achieve low development and production costs. Manage partners in Greece, Taiwan, and mainland China.

* Evaluated and selected various tools, including Mentor Questa, SystemVerilog for simulation, Xilinx ISE, Agile PLM,

and Hyperlinx.

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Jeffrey C. Smith (Resume)

Sr. Technical Staff and Development Director

10110 Doubletree Ranch Rd. 480-***-****

Home

Scottsdale Az 85258 408-***-****

Mobile

E-mail: ************@*****.***

Special Projects Director

West Coast Developers San Diego, CA; 2003 to 2008

Specializing in IP and Green Systems. Rebuilt smart homes from the ground up. Worked on all stages of multiple

Projects, & Custom Remodels (Custom Architecture). Managed architecture and installation of Wiring, Entertainment,

Networks, and custom Green systems Utilizing Cisco, EMC, and AT&T Products.

Sr. Strategic Product Architect and Applications Manager

Integrated Device Technology (IDT) Santa Clara, CA; 1991 to 2002

* Responsible for development of all semiconductor products, and test boards for both engineering. Created

development and review processes to ensure high quality, low cost, high yield designs.

* New Product Architecture of 100's of devices including: Std. & Sync. SRAMs, Power PC/MIPs/P5 Burst SRAMs,

Multi port SRAMs, and Specialty Memory Switch Controllers with Codecs and DSPs, cache memories (cache, tags, &

monolithic controllers w/ on chip cache), and switch memories (input & output cell/packet, central multi ported,

controller queuing logic, & generic multi ported memories with DRAM cores). Developed Processes with R&D for

3.3V/2.5V/1.8V products and architecture for die size, power, & speed.

* Developed several agnostic switch memories and controllers; supporting various interfaces, including ATM, Frame

Relay, and E Net interfaces utilizing Validated patented congestion management algorithms. Initiated development of

next generation higher density L2 gateway switches,1Gb Ethernet interfaces with congestion management functionality,

PHYs and SARs, and Network Processors.

* Formed development team, consisting of electrical engineers, test engineers, board designers, ASIC/FPGA engineers,

Verilog verification engineers, engineering services including electrical device validation testing (EDVT), and technical

documentation. Setup development lab. Worked closely with both executive and cross functional team members,

including CEO, CFO, manufacturing test, sales, marketing, and Design/Test/R&D engineering.

* Conversed with customers to fully understand network issues and worked closely in cross functional teams to create

solutions that solved those issues. Developed key customer alliances and partners.

* Improved employee morale Improved employee performance from low output into high performance to produce

products from concept to first customer shipments; drove engineering to complete entirely new designs in a very

aggressive time periods. Worked across separate Business Unit development teams and obtained sufficient support to

achieve project success.

* Created and presented presentations to executive staff, Product and Marketing Vice Presidents, and Customers.

Developed budgets Maintained lean organization while maximizing productivity.

* Developed 1 to 5 year next generation specialty memories and communication switch products development and

technology roadmaps.

* Created and architected flexible designs to enable re use across multiple products with future expansion capabilities

while balancing cost and development complexity.

* Developed the world's first System on a Chips (SOCs) approximately 1.5 years before the next fastest competitor

* All projects met committed dates with high reliability and quality, much lower than expected field failure rates, at

significantly lower cost products than equivalent products in other business units. Direct involvement in Products

3

Jeffrey C. Smith (Resume)

Sr. Technical Staff and Development Director

10110 Doubletree Ranch Rd. 480-***-****

Home

Scottsdale Az 85258 408-***-****

Mobile

E-mail: ************@*****.***

achieving over $100 Million US annual revenue.

• Numerous Customer trips to Japan, Korea, UK, France, Germany, and many other Asia and European sites.

Electronic Design Specialist and Software Architect

Boeing Military and Electronics Seattle, WA

1985 to 1990

Mil. Grade of 16, a DX 10 Priority, and Top Secret w/ multiple Secret Access Security Clearances)

• Team lead managing the Interactive Touch Screen Avionics and Laser Disc Recorder Instrumentation. This was an

integrated product for the B1 Bomber SRAM2 Missile Upgrade. The system used highly integrated board and system

design utilizing embedded MIPs processors, video HW support, Selective Data Recording with Packetization and

Redundancy, and multi LRU design.

• Manage touch technology transfer from Mega Tech Monitors and Simulators, and integration into the B1 Bomber.

Included IR laser module, Radar, custom transceivers, and FPGA and CPU based processing.

• Responsible for architecture definition, resource management, detailed implementation, and sub contract management.

• Managed the complete development cycle from concept to production, including all development, production

processes, tooling and software. Responsible for delivery and implementation Architecture, Design, Layout, and Test.

• Lead Manager over a team of 5 design/software/firmware engineers and 14 technicians, and manage an annual budget

of ~$100M.

• Internal design and delivery of a 4MGate digital ASICs, 14 system designs (LRUs), and Interfaces to the B1B.

• Wrote, presented, and implementing New Military Contract Proposals to SAIC & SPO's. Profitability exceeded

~$500M.

Lab Instructor & Manager

NAU's Engineering MIS Flagstaff, AZ; 1983 to 1985

Prior to 1985: Managed accounts for a $10M+ power transmission company during high school for 3.5 years; followed

by a manager position for a major record company which lasted through my first 2 years of college. Then during school

at Flagstaff I managed a resort's maintenance department for 1 year, followed by a summer job for Intel's VLSI test

division writing & implementing test programs on custom S90 testers. Also 1.5 years as manager at NAU's Engineering

MIS department, while I was simultaneously a professor's aid.

Education

MSEE in SoC & P/S Design & Architecture

Boeing WSU Seattle, WA

March 1985 to March 1987

BSEE in System architecture & design

Northern Arizona University Flagstaff, AZ

4

Jeffrey C. Smith (Resume)

Sr. Technical Staff and Development Director

10110 Doubletree Ranch Rd. 480-***-****

Home

Scottsdale Az 85258 408-***-****

Mobile

E-mail: ************@*****.***

August 1980 to January 1984

Computer Science Engineering in F/W & S/W Design & Architecture

NAU Flagstaff, AZ

August 1980 to January 1984

PATENTS & PAPERS

Patent – Sequential Access Random Access Memory (SARAM).

Patent – Semaphore Logic in DPRAMs and Shared Memories.

Patent – Semaphore Expansion with Interrupts.

Patent – Shared Memory Mail Boxes.

SRAM Conference Papers – Sync. Burst SRAM and Tag memory Papers.

SMP Conference Papers –SARAM Basics, SARAM – New Type of Memory, SARAM E Net,

Shared Memory, & Bank SwitchableTM Memory.

Switch Conference Papers – SwitchStar Concepts, SwitchStar Larger Switches, & SwitchStar

E Net.

SRAM Application Notes – Multiple SRAM, Tag, and SBSRAM A/Ns.

SMP Application Notes – Intro to Multi Port Memories, Using 7024/7025 to Match System Bus

Widths, Dual Ports Simplify PC to TMS320, Dual Port Interrupt Expansion, Dual Port w/

Semaphore Arbitration, What is a Sync DPRAM, Sync. Dual Port for DSP & Communications

Applications, Using the 7052/7054 in DSP & Matrix Applications, Intro to the 4 Port, 4 Port

Semaphores, and SARAMTM.

Switch Application Notes – Using 77V011 in Small Access Switch, Sub Tending using Priority

Levels, Data Path Interface Examples, SwitchStar Cell Bus, DPI to Utopia, SwitchStarTM User

Manual, and SwitchStarTM Sub Tending.

COMPUTER SKILLS and TOOLS

Mentor & Sun Synopsys & Cadence, Linux, Windows, P Cad, PSpice, Orcad, Mentor Pads, Altium Designer, Allegro

Designer, AutoCad, Metlab, Verilog, VHDL, C, C++, HTML & CSS, and Java. General: Microsoft Word, Excel, &

PowerPoint; Canvas, Adobe Design, & CorelDraw.

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