Software QA Analyst/Engineer

Sheshank Kodam

*** *.******* **, #***

Indianapolis, IN 46202

******@*****.***,

********.*****@*****.*** 617-***-****

OBJECTIVE

Looking for a challenging full-time position that offers opportunities for learning and growth in the Computer and Electrical Engineering fields. In particular, the interactions of computer systems, software, graphics and hardware.

EDUCATION

Master in Electrical and Computer Engineering GPA: 3.5/4.0

Purdue School of Engineering & Technology, IUPUI

Thesis: A New GPU Based Deadlock Detection Algorithm (GP-DDA) for Multi-Unit Resource Systems

Expected Graduation: December 2011

Bachelor of Technology in Electronics and Instrumentation Engineering GPA: 3.6/4.0

Jawaharlal Nehru Technological University, JNTU

Graduation: May 2009

TECHNICAL SKILLS

Programming Languages: CUDA, C, C++, C#, Java, VHDL, Verilog HDL, OpenCL, Micro-processor Interfacing (MASM), HTML, CSS, JavaScript

Software Systems: MATLAB/ Simulink, Microsoft Office, Pro/Engineer CAD, Adobe CS5 Tools, Xfig

Operating System: Microsoft Windows Family, Linux Family, UNIX

PROFESSIONAL EXPERIENCE

Research Assistant, IUPUI January 2009 – Present

Developed a novel GPU-based Deadlock Detection Algorithm (GP-DDA) for multi-unit resource systems

- Implemented an optimized CUDA C and C++ code for GP-DDA

- Implemented Instant Multi-unit Deadlock Detection Unit (IMDDU) on GPU using CUDA and C++

- Designed CUDA architecture for Single-unit Dead Lock Detection Algorithm (OSDDA)

- Gained experience in CUDA C, C++, C, algorithms, latex, Xfig, and writing IEEE publications

Intern, IUPUI June – August, 2010

- 3D Visualization of the medical ultrasound images to detect cancer cells

- Implemented warping algorithm using MATLAB and OpenCL to estimate the depth from stereo images

- Worked on C++ programs based on markov random field energy function: Graph cuts, Belief propagation and Iterated Conditional Model (ICM)

Technology Consultant, IUPUI September – December, 2009

- Trouble shoot network related hardware and software problems

- Acquired experience in working with various Operating Systems

- Gained experience in collaborative work

Intern, Indian Space Research Organization (ISRO), Dept. of Space, India January – May, 2009

- Developed ground level Test Pattern Generation of Radar Imaging Satellite (TPG-RISAT)

- Simulated Synthetic Aperture Radar (SAR) sensor data for testing TPG-RISAT

- Used hardware programming tool – Altera MAX+PLUS II VHDL

Intern, Indian Space Research Organization (ISRO), Dept. of Space, India July – December, 2008

- Gained experience in Altera MAX+PLUS II VHDL

- Developed frame synchronous code in VHDL for Random Binary Sequence generator.

- Used hardware programming tool – Modelsim VHDL

PUBLICATION/THESIS

GP-DDA: A New GPU-Based Deadlock Detection Algorithm for Multi-Unit Resource Systems, IEEE Computer Architecture Letters

A novel deadlock detection algorithm for multi-unit resource systems is developed and implemented using GPUs. Tasks included adapting the CUDA architecture and programming concepts. An optimized CUDA C code for GP-DDA is implemented on a heterogeneous CPU-GPU system, where the CPU captures the information of the events occurring in the OS and the GPU performs the computations to the check the deadlock condition in the system. Using GP-DDA, deadlock state in a system can be identified at instant time.

Thesis advisor: Dr. Jaehwan John Lee

ACADEMIC PROJECTS

Computer Architecture project

- Simulated ARM 9 architecture in user mode using Mhetero frame work

- Implemented data processing instructions of ARM 9 with 5 stage pipelining using C#

- Gained experience in MIPS and ARM architectures

Face Recognition

- Performed face and iris image classification through Principal Component Analysis (PCA) and Linear Discriminant Analysis (LDA) using MATLAB

- Testing and cross-validation of face and iris images from 40 subjects

- Performed hyper-spectral image classification using Principal Component Analysis (PCA)

Integrated Nano-Technology

- Designed and fabricated CMOS using lithography

- Designed and evaluated the performance of micro mixer and mirror design using Coventer

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