Electrical Engineer Design

Rushin Patel

** ****** ***, ***** # ***, Cell no. : 973-***-****

San Jose, CA 95110 Email:*************@*****.***

Objective: Seeking for a position of electrical engineer and want to work with a progressive and forward

thinking company where I can use my skills.

Education:

M.S. in Electrical Engineering

San Jose State University, San Jose, California GPA (3.60/4.0) (Jan 2008 – Dec 2009)

B.E. in Electronics & Communication Engineering

Gujarat University, Gujarat, India GPA (3.96/4.0) (Aug 2003 – Jun 2007)

Skill:

Tools familiarity: Cadence design environment (virtuoso composer schematic, virtuoso layout editor),

Synopsys Design Tools, VCS Compiler, Xilinx ISE, ModelSim SE

Coding skills: System Verilog, Verilog HDL, Assembly Language programming.

Non-comprehensive: C language, MATLAB, Basic knowledge of C++, Perl

Operating Systems: Windows 95 / 98 / 2000 / XP / Vista, UNIX, Mac OS

Communication Skills : Bilingual: English/Hindi, Excellent verbal and oral communication skills

Relevant Coursework:

Advance Digital System Design & Synthesis High Speed Circuit Design

Advanced Computer Architecture Mixed Signal Circuit Design

ASIC CMOS Design Semiconductor Devices Physics

SoC Design with System Verilog

Training:

Solar Panel Tracking System, F.K.Electronics, India (B.E. Final Year) (Team members: 2)

-Main aim is to achieve maximum output voltage across solar panel.

-By RTC, Position Sensor & 89C52 calculate the angle of rotation from the current position of panel.

-With help of stepper motor, rotate the panel according to required position to get maximum o/p.

-About 60% increase in power with respect to fixed panel.

Master Level Projects:

ATM Switch using system Verilog (Individual Projects)

- Create the ATM port interface; complete the port definitions for Interface module.

- Using interface protocol combining Octopus module with different modules.

- All other modules are given by Synopsys and created test benches to test the modules.

The Analysis of Area-Delay & Power-Delay Tradeoffs in Addition Circuits (Individual Projects)

- Comparison of RCA and CLA in terms of area and power delay for 8,16,32,64 bits.

- Work is verified using Synopsys synthesizer on two different libraries.

- Result explored correlations between area-delay & power-delay for both implementations.

Speculative Tomasulo’s Algorithm in Verilog (Team members: 2)

- Modules: Reorder Buffer, Reservation station, common data bus, 1 KB memory, instruction

decoder, functional unit, store bus, control unit.

- Instruction implemented: Arithmetic, load, store and branch instructions.

- Checked using printable o/p with self-generated text file & Tested algorithm with complex test cases.

Design of 32-bit Program Counter Using Dynamic Logic (Team members: 2)

- Design technology and specification: 45 nm, 2 GHz frequency, 1 V Power supply.

- Developed PC that performs stack, hold & jump operation with Schematic, layout and LVS.

- Design was implemented using 5-phase clocking and latency was 11 phase.

Design of 8-bit Pipelined Analog to Digital Converter (Team members: 3)

- Design technology and specification: 0.18 um TSMC, 1.8 V Power supply, 0.6 MHz Sampling rate.

- Schematic, layout, analog extracted and LVS done.

- Blocks: Op Amp, Sample & Hold circuit, clock comparator, 1 bit MDAC, balanced switch, current mirror.

Design of Phase locked loop (Team members: 3)

- Design technology and specification: 90 nm GPDK, 1.2 V Power supply.

- Simulator: Spectre Spice using Virtuoso analog Environment.

- Blocks: Charge Pump, Divider, PFD (Phase Frequency Detector), Low pass filter.

References: Available upon request.

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