Post Job Free
Sign in

Software Engineer - Project Manager

Location:
hyderabad, AP, India
Salary:
30k
Posted:
June 17, 2011

Contact this candidate

Resume:

BABY PRIYANKA. TELAGATHOTI

Contact #: 994-***-****.

*******************@*****.***

CARRER OBJECTIVE:

Aspiring a suitable position in a progressive organization that gives me an opportunity to explore myself and contribute to the development of the organization.

Self-starter, able to work independently with less supervision. Team player – Able to establish good rapport and efficient working relationships with peers, superiors, and users of various social, professional, and cultural backgrounds.

EDUCATIONAL QUALIFICATION:

• Passed the Master of technology in VLSI System design from Shri Vishnu Engineering College for Women (2008 to 2010 October) affiliated to JNTUK with aggregate of 70%.

• Passed the Bachelor of technology in Electronics and Communication Engineering from Jyothishmathi Institute of Technology and Sciences (2004 to 2008) affiliated to JNTU with aggregate of 61%.

• Passed Intermediate from Morning Star Junior college (2002 to 2004) of aggregate of 71%.

• Passed SSC from St.Ann’s Girls High School (2001 to 2002)with aggregate of 71%.

Technical skills:

Software Languages: C.

Hardware descriptive languages: VLSI,VHDL,VERILOG,ASIC DESIGN, FPGA,DEGITAL DESIGN,CMOS,PCB Layout design.

EDA tools: Modelsim, Xilinx ISE (FPGA implementation tool)Xmanager,

M.TECH project details:

Title : Implementation of JPEG Encoder Using Spartan-3 FPGA.

Platform : VLSI

Team size : one

Duration : 8 months

The main aim of the project is implementation of a JPEG encoder that exploits minimal usage of FPGA resources. The encoder compress an image as a stream of 8*8 blocks with each element of a block applied and processed individually .The zigzag unit typically found in implementations of JPEG encoders is eliminated. The division operation of the quantization step is replaced by a combination of multiplication and shift operations. The encoder is implemented on Xilinx SPARTAN-3 FPGA and is benchmarked against two software implementations on four test images. It is demonstrated that it yields performance of similar quality while requiring very limited FPGA resources. A co emulation technique is applied to reduce development time and to test and verify the encoder design.

Keywords:Imagecompression,JPEGencoder,hardwareimplementation, FPGA.

Technologies: VHDL, XILINX SPARTAN-3 XC3S200

B.tech Project details:

Title : HOTSPOT INFO SYSTEM

Platform : Embedded system

Team size : Five

Role : Coding and Documentation.

Duration : 6months

The aim of the project is the major problem for travelers is to collect local Information about the route they travel specifically in long highways. In this Project we designed a wireless based kiosks. The user can request the required information through the LCD display and keypad. The kiosks on receiving the request process it, and populate the required information on LCD display.

Technologies: ALP, Atmel AVR Studio 3.5.3

Personal Skills:

• Willing to work in challenging environment

• Aspiring to learn new things

• Self-motivated

Achievement:

• Presented a paper on Digital Image Capturing & Processing at State Level.

• Presented a paper in the Technical Paper Presentations in “Technovision”

• Secured second prize in essay writing at school level.

• Participated in cultural activities at school and college level.

Hobbies:

• Freaking out with friends.

• Working in group.

• Organizing events.

• Browsing.

LIST OF PAPERS PUBLISHED

• Published a paper on “JPEG encoder using SPARTAN-3 FPGAs” in International Conference on Signals, Systems and Security ICSCI-2010.

• Published a paper on “Discrete cosine transforms Vs Discrete wavelet transform: An Objective Comparison Technique For JPEG Controller” in National Conference on Signals,Systems and Security NCSSS-2010.

• Published a paper on Floating point FPGA Vs Coventional FPGAs:an objective comparison of FPGA resources for modeling performances on NCSSS-2010.

• Participated in VLSI workshop on Advanced digital design tools in the Shri Vishnu engineering college for women.

Personal profile:

Name : T.BabyPriyanka

Father’s name : T.Adamu

Gender : Female

Date of birth : 16-08-1987

Contact Address : flat no:515

Block-A

Dollfine estates

Near miyapur police station

Hafeez pet village

Hyderabad

500050

Declaration:

I here by declare that all the above stated information is true to the best of my knowledge and belief.

Place:

Date: (T.BABY PRIYANKA)



Contact this candidate