Graduate Technical Intern
Resume:
ASHISH SHARMA
A-**, sector-**, Noida -******
Contact: 096********; Email: *************@*****.***
PROFILE
• Worked as an INTERN in TR&D Group in ST Microelectronics from JULY 2011 to JUNE 2012.
• Qualified Masters in VLSI-CAD Design with 8.25 CGPA from Manipal University.
• Steep knowledge in Digital Circuit Design Concepts and ASIC Flow.
• Ability to write/understand the RTL Design in Verilog.
• Experience in design debugging, fixing bugs and scripting.
• Knowledge in Verilog based Testbench Development and Code Coverage
• Basic knowledge of CMOS.
• Ability to work in a team and as an individual.
• An effective team player with excellent planning and execution skills coupled with a systematic approach and quick adaptability.
WORK EXPERIENCE
Title Process Monitor IP (PROMIP) (STMicroelectronics)
Technology CMOS28nm, C32nm, C45nm, C65nm, M10ULP
Synopsis It can be used at wafer level testing to ensure that the chip is within the predefined process limits, it measures the performance in terms of speed and leakage.
Responsibility Development of Verilog based Verification Environment by mainly using Directed Testbench
Approach. Tested the IP with all possible type of corner case tests to stress the design to be free
from bugs. Code Coverage includes FSM, BLOCK, TOGGLE and expression. Initially code coverage
was 81%. It is improved up to 94% in stress testing.
Language, Tool Verilog (HDL), Design Compiler (Synopsys), NC-Verilog (Cadence Incisive Enterprise Simulator).
Title PMB CAD DATA GENERATION AUTOMATION (STMicroelectronics)
Technology C28nm,C45nm
Synopsis There are two parts of CAD data generation, netlist extraction and data extraction. The main motive is to calculate MTBF (mean time between failures) as a result for different PVTs. For this purpose “.CIR” files have been created and then ELDO simulation is done.
Responsibility Responsible for writing TCL script for netlist extraction and data extraction. With the help of TCL
script, netlist has been extracted for multiple cells on different PVTs (process, voltage, and
Temperature) and in data extraction MTBF is calculated by the help of TCL and ELDO tool. There is
0.3V to 1.3V variation in voltage, -40C to 125C temperature variation for different processes.
Language, Tool TCL, ELDO.
TECHNICAL SKILLS
• Tools VCS, NCSIM, ICCR (Coverage analysis), ELDO, SPYGLASS,FORMALITY
• Model Simulator Magic, HSpice.
• Hardware Description Language Verilog
• Synthesis Design Compiler(Synopsys)
• Scripting Language TCL, Perl, Shell
ACADEMIC CREDENTIALS
Class/Course Name of Institute Board/University Year of Passing Marks%
MS(VLSI-CAD) Manipal Centre for Information Science Manipal University, Manipal 2010-12 8.25 CGPA
B.Tech
(Electrical and Electronics Engineering )
Hindustan Institute of Technology, Greater Noida
Uttar Pradesh Technical University, Lucknow
2005-09
68.0
Intermediate S.K.S.V.M. Shahjahanpur
Uttar Pradesh Board 2004 68.4
High School S.K.S.V.M. Shahjahanpur
Uttar Pradesh Board 2002 62.67
Projects during M.S
Title An Embedded True Random Number Generator for FPGAs in VERILOG
Synopsis Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. It produces random bits at speeds of up to 0.5 Mbps with good statistical characteristics.
Responsibility Understanding of the design behavior and FPGA Concept and its implementation in terms of Verilog. Development of Verilog based Testbench to verify the design by writing number of testcases.
Language, Tool Verilog, VCS(Synopsys)
Title Arbiter(under “WHIZCHIP TECHNOLOGY” Bangalore)
Synopsis Arbiter facilitates the connection between master and slave for proper communication. MASTER and SLAVE is a model of communication where one device or process called Master has unidirectional control over one or more devices called Slaves. In this project a MASTER is elected from a group of eligible devices, with the other devices acting in the role of slaves.
Responsibility Understanding of Master-Slave concept and the implementation of Arbiter design in Verilog. Development of Verilog based Testbench to verify the Arbiter design by writing number of testcases of master-slave scenarios and arbiter cases.
Language, Tool Verilog, VCS (Synopsys)
Title Universal Asynchronous Receiver and Transmitter (UART)
Synopsis UART, In the asynchronous transmission the data is not sending at all times. When no
data is send the line remains in the High state. When the data is to be transmitted then the Low start bit is sent before the data byte and the receiver detects that bit and accepts the data byte. At the end of the data a High stop bit is send which tells the receiver that the data byte is ending here.
Responsibility Understanding of the UART Protocol and its implementation in Verilog. Development of Verilog based Testbench to verify the UART implementation.
Language, Tool Verilog, VCS (Synopsys)
Project during Under Graduation
Title Automatic Lighting System(Mini Project)
Synopsis Not only save the valuable energy, it can be used for security reason, to check the total persons to be entered or exit. It takes over the task of switching on and switching off the lights automatically when somebody enters or leave the room during darkness. It is basically Automated blinds control based on sensor reading.
Responsibility Understanding of the project, and working of ICs and sensor. Mounted the ICs on PCB board.
Hardware Electronic components,555 Timer IC
EXTRA CURRICULAR ACCOLADES
• Gave 1st seminar on “Touch Screen Technology” (Capacitive) in 2010
• Gave 2nd seminar on “MORPH Technology” in MCIS
• Participated in chess competition in inter-branch competition held at college
• Received Best player award in Volleyball Championship at District Level.
Name : Ashish Sharma
Father’s Name : Jagannath Sharma
Gender : Male
Date of Birth : 16th march 1986
Known : English, Hindi
Status : Single
Hobbies : Playing Cricket, Volleyball, Chess.
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