CAREER OBJECTIVE:

Seeking a challenging environment where my skills are highly enriched and useful for the growth of organization and myself.

PROFESSIONAL TRAINING

An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt Ltd., Hyderabad since August 2011 to till December 2011.

WORKING EXPERIENCE:

• Simpli5NG Semiconductors : (May-2010 – Aug-2011)

Designation : Intern and Design Engineer

Job Profile : Worked as RTL Front End Design Engineer at simpli5NG Semiconductors Pvt Ltd. (Front-End)

SUMMARY OF QUALIFICATIONS :

• B.Tech. in ECE from DRK College of Engineering & Technology, Bowrampet, Hyderabad, affiliated

to J.N.T.U, Hyderabad during 2006-2010.

• Intermediate from Sri Chaitanya Junior College, Hyderabad during 2004-2006.

• X (SSC) from Vidya Bharathi High School, Hyderabad during 2003-2004.

SOFTWARE EXPOSURE:

Operating system : Windows, Linux, Unix

Languages : C

Scripting Languages : TCL (Basics)

PNR Tools:

• Cadence SOC Encounter : Floor Planning, Place & Route and CTS

• Encounter Timing System : Static Timing Analysis and Crosstalk Analysis

• RTL Compiler : Logic Synthesis

• Assura : Physical Verification

• Virtuoso : Custom layout

Front-End Skills:

• HDL Languages : VHDL and Verilog.

• EDA Tools : Xilinx ISE ,Active HDL ,MATLAB , Model SIM

• Designing Skills : RTL Designing, Xilinx FPGA Prototyping.

LOGIC SYNTHESIS:

Project 1 : 8-Bit synchronous counter with an asynchronous Reset.

Tools : RTL Compiler

Clocks/Frequency : 2/200MHz

Role: Prepared Constraint file, TCL file, Performed Wireload and ZeroWireload model.

Project 2 : 256-bit counter

Tools : RTL Compiler

Role: Calculated the Clock Frequency, Prepared Constraint file, TCL file, Performed Wireload and ZeroWireload model.

LAYOUTS

Using Folding Technique Designed Layouts for Basic gates like Inverter, NAND, NOR.

Tools : Virtuoso

BACK-END PROJECTS :

Project 1 : PCI-DATA (TOP LEVEL)

Tools : SOC Encounter, ETS.

Gate count : 21,000

Blocks /Cells /IOs : 12/26640/120

No. of Clocks : 7

Frequency : 150 MHz

Technology : UMC 0.18 micron

Role: Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail Route , Power Analysis , Timing analysis , CTS .

Project 2 : Brx-Top (BLOCK LEVEL)

Tools : SOC Encounter, ETS.

Gate count : 11,000

No. of Clocks : 3

Frequency : 333 MHz

Technology : UMC 0.18 micron

Role: Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail Route , Power Analysis , Timing analysis Observed the problems when metal stripes and rings are placed at lower metal layers.

Project 3 : (BLOCK LEVEL)

Objective : Timing Driven Layout

Tools : SOC Encounter, ETS.

Gate count/Area : 3,10,736/ 1582334.9 um^2

Macros /STD Cells : 12/28703

No. of Clocks : 17

Frequency : 200MHz

Technology/Layers : TSMC 0.13 micron/5 Metal Layers

Role: Performing sanity check , Design import , Floor Plan, Placement , Trail Route , Power Analysis , Timing analysis , CTS ,Detailed Routing.

• Have a block level place and route exposure on 130nm and 90nm technologies.

• Expertise in Floor Planning, Place & Route, Clock Tree Synthesis, Timing Closure, SI Analysis & DRC/LVS.

• Sound knowledge in Timing Analysis & Crosstalk Analysis .

Front End RTL Development:

Project I

Title : Variable Length encoder.

Objective : Efficient Image data compression and transmission.

Organization : Simpli5NG Semiconductors (Pvt) Ltd, Hyderabad.

Technology/Tool : Spartan®-3E FPGA , Xilinx ISE 9.2i.

Project II

Title : Object Motion Tracking System

Objective : Tracking the moving object by calculating the displacement of object.

Organization : Simpli5NG Semiconductors (Pvt) Ltd, Hyderabad.

Technology/Tool : Spartan®-3E FPGA , Xilinx ISE 9.2i.

Project III

Title : Low power H.264 for mobile applications

Objective : Implemented H.264 encoder for low power.

Employer : Simpli5NG Semiconductors (Pvt) Ltd, Hyderabad.

Tool : Xilinx ISE 9.2i

Technology : Xilinx Spartan -3E-XC3S500 Board

Project IV

Title : CAVLD

Objective : Creating a memory less architecture for CAVLD using Tree structures

Employer : Simpli5NG Semiconductors (Pvt) Ltd, Hyderabad.

Tool / Technology : Xilinx ISE 9.2i / Xilinx Spartan -3E-XC3S100 Board

ACHIEVEMENTS:

• Organised National Level Paper Presentation events during Engineering.

• Participated in National Level Paper Presentations held in PIRM College of engineering and technology on topic Code Compression.

• Presented a Seminar on Ozone Layer Depletion for creating Environmental awareness in college.

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