Project Design

CURRICULUM VITAE

DEEPTHIMAHANTI SAI PRAVEEN Bangaluru

E-Mail: ******.****@*****.*** Cell: +91-741*******

Career Objective:

Seeking a challenge and responsible position for professional growth and advancement where initiative and hard work is encouraged and rewarded.

Educational Qualifications:

Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore

B.Tech (Electronics and communication Engineering) from Akula SreeRamulu college of Engineering, Tanuku (Affiliated to JNTU Kakinada) in 2011 with 63%

Intermediate (MPC) from Board of Intermediate Education in 2007 with aggregate of 89.9%

S.S.C from Board of Secondary Education in 2005 with aggregate of 70.6%

Technical Skills:

Operating Systems : Windows XP / Windows 7/ Redhat Linux / Ubuntu

Programming Languages : Basics in C, C++.

EDA Tool : Xilinx Modelsim and Questasim.

Hardware Languages : Verilog & System verilog.

Verification methodologies: Coverage Driven Verification, Assertion Based Verification.

TB Methodology : VMM from Synopsys, Basics in UVM

Knowledge : RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis.

Strengths:

Very enthusiastic and a quick learner.

Confident to work in a Team.

Ability to quickly grasp technological aspects and willing to learn.

Having Good analytical ability.

Achievements & participations:

• I made my mini project with extremely small price of 80.Rs

• Participated in Project presentations held at nearby colleges

• Leaded my team for the main project.

Main Project:

Project Name : Diagnosis of faulty CLB’s in FPGAs

Software used : DSCH, MICROWIND

Duration : 4 Months

Role : Designing of CLB in DSCH.

Description : Field programmable gate arrays (FPGAs) have been used in many areas of digital design. Because FPGAs are programmable, faults in them can be easily tolerated once fault sites are located. However, diagnosis of faults in FPGA has not yet been explored by researchers. A new methodology for the testing and diagnosis of faults in FPGAs is presented based on built-in self-test (BIST).

Test time depends only on the number of faults, and is independent of the chip size. With the help of this technique, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced.

We used 4 bit comparator to compare the two CLB’s to find the faults in the DSCH. And we used Microwind to get the Power Dissipation Graphs for Stuck at Faults

SPI Controller Core - Verification

HVL : SystemVerilog

EDA Tools : Modelsim, Questa -- Verification Platform

Description : The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock.This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register.The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – Verification

HVL : SystemVerilog

EDA Tools : Modelsim, Questa -- Verification Platform and ISE

Description : The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Experience:

Aug-2011 – Feb-2012, Maven Silicon, VLSI Design and Training Center

Personal Profile:

Father’s Name : D.V.V.Laksmi Narayana

Nationality : Indian

Date of Birth : 27th - july-1989

Languages Known : Telugu, English

Hobbies : Chatting with my memories, dreaming about new.

Declaration:

I here by declare that all details furnished above by me are true to the best of my knowledge and my career.

Date: (D Sai Praveen)

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