Six years experience in logic design and verification

Farhan I. Mansoor

***** ** ***** *******

Tigard, OR 97224-1834

***********@*****.***

Cell 513-***-****

Home 503-***-****

SUMMARY

Electrical Engineer with six years experience in logic design and verification seeking opportunities to further career. Also interested in entry-level positions for:

- printed circuit board design

- analog/IC design

- embedded firmware development

- software development

ELIGIBILITY

United States citizen

RELOCATION PREFERENCE

Willing to relocate nationwide at own expense

WORK EXPERIENCE

12/2006 - 02/2009 Rockwell Collins Head-Up Guidance Systems, Portland, OR

Electrical Engineer

- Followed DO-254 (Design Assurance Guidelines for avionics hardware) processes for development of Model 6250 Head-Up Guidance System

Hardware Development

- Derived FPGA requirements and ensured all system-level requirements were implemented using requirements trace matrix

- Documented design requirements and implementation

- Used Xilinx Virtex-5 for FPGA platform and performed design entry using Xilinx ISE 10.1.sp3

- Implemented FPGA Power-on, Reset and Clock Requirements

- Designed FPGA interface with external ARINC 429 Transmitter and Receiver, Fiber Channel AV Optical Transceiver, LVDS SERDES Transmitter, RS232 Transmitter and Receiver, A-D and D-A Converters, Heater and Fans, Pulse Width Modulation, Flash Memory and Thermal Sensors

- Performed FPGA bring-up in lab using logic analyzer and oscilloscope

- Implemented design fixes as identified by verification and confirmed

integrity in lab

- Performed version control of RTL code using Subversion (TortoiseSVN)

FPGA Verification

- Studied Design Under Test and presented test plan

- Verified bus addressing scheme, FPGA R-W access restrictions, unused functions, FPGA-FPGA communications, status updates on registers, direct-indirect addressing, arbitration between multiple requesters, reset and power-on operation, fault status reporting, word-size selection, FPGA-Processor communications, EDAC, Flash / NVRAM / SSRAM accesses, FPGA-USB communications, timeouts and Interrupt handling

- Performed code review and identified incorrect coding practices

- Wrote test-benches using VHDL

- Performed simulations using Questasim 6.3e

- Studied Actel ProAsic3 architecture for timing analysis

- Identified RTL modules with less than 100% code coverage and justified reason for acceptance

- Documented verification test plan and test report

- Ensured all hardware requirements were covered using trace matrix

02/2001 - 01/2003 Cirrus Logic, Austin, TX

Verification Engineer

- Responsible for RTL verification of CS4202 stereo audio codec

- Assisted in defining verification methodology for team; identified steps to be executed for the Device Under Test

- Wrote verification test-plans; developed system-level test-benches using Verilog and Assembly

- Ensured completion of verification efforts within schedule constraints

- Informed hardware designers of corrections to be made to requirements and implementation documents

01/1999 - 12/2000 IBM, Poughkeepsie, NY

Development Engineer

- Assisted in implementation of the Buffer Control Element for the IBM eServer z900 processor

- Presented module design concepts; implemented RTL design using VHDL

- Assisted with system-level verification efforts; debugged failing regression runs

- Improved testfloor efforts for mainframe bring-up; organized team efforts

SKILLS

Hardware Development

VHDL, Xilinx ISE 10.1.03, Mentor Graphics Questasim 6.3e, Subversion (TortoiseSVN), Verilog, DOORS, Debussy

Protocols

USB, I2C, RS232, LVDS, SPI, VESA CVT, RS170A, DVI, ARINC 429, ARINC 818, PPC603

Error detection

EDAC, CRC, SEU, Triple Modular Redundancy, LFSR

Processors

Freescale PowerPC MPC7410, Motorola MC68000

Programming

Perl, MATLAB, C, Assembly

EDUCATION

01/2004 - 05/2006 Texas A&M University, College Station, TX

M.Eng, Electrical Engineering

- Wireless Communications, Modulation Theory, Spread-spectrum and CDMA, Time-frequency and wavelet analysis, Digital Signal Processing, Information Theory, Estimation and Detection Theory, Statistical Communication Theory

09/1994 - 12/1998 New Jersey Institute of Technology, Newark, NJ

B.S., Electrical Engineering

- Graduated Summa Cum Laude (2/56 in EE department)

- Tau Beta Pi (member)

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