ASIC Design Engineer

Arpita Kadakia **** Preston Road, Plano, TX, *****

(Permanent Resident, Green Card Holder) Mobile: 928-***-****, Email *********@*****.***

OBJECTIVE:

Seeking an Entry Level Full Time position in the field of Electrical Engineering with opportunity to use skills in ASIC/FPGA Design.

EDUCATION:

Masters in Electrical Engineering, University of Nevada Las Vegas, Dec 2010. GPA 3.8/4

Bachelors in Electronic Engineering, Mumbai University, India, June 2007. GPA 8.5/10

Diploma in Electronics & Communication, Mumbai University, India, June 2004. GPA 8.7/10

WORK EXPERIENCE:

Teaching Assistant, Digital Design Laboratory, UNLV Aug 2009 –Dec 2010

Assisted students in their project work, grading assignments, holding TA hours and leading lab sessions.

Quality Assurance Engineer, INgage Networks, Naples, Florida Jan 2008 to Aug 2008

Duties included load/performance, security and browser compatibility testing.

RELEVANT SKILLS:

Programming Languages: VHDL, Verilog

CAD Tools: Xilinx ISE 11.1, Quartus II 7.1, Active HDL 7.1, ModelSim-Altera 6.1g, Visual Studio 2008

FPGA Families: Virtex -IV, Sparten 3E

Processors: Picoblaze, 8051

Experience with Version Control Software (Subversion) and Bug Tracking System (Bugzilla)

MASTER’S THESIS

Data routing in multicore processors using Dimension increment method

• Designed an architecture consisting of multiple instances of Picobalze and routing channels to efficiently route data among the various processors employing the dimension increment method.

• The hardware was developed using VHDL on Xilinx ISE 11.1 and the design was implemented on a Virtex 4.

RELEVANT PROJECT

ZBT SRAM Controller

Implemented ZBT SRAM with no bus latency. This device used full bandwidth because and did not require turnaround cycles i.e., idle cycles between read and write operations. The SRAM Controller was simulated using VHDL on Xilinx ISE 11.1

ACTIVITIES

• Fund Raising Chair, Indian student association, UNLV Aug-09- Jan10

• Vice President ,Indian student association, UNLV Jan10- Dec 10

RELEVANT COURSEWORK

Hardware Description Lang: VHDL, Reliable Design Digital System, Interconnection Network Parallel Proc, Synthesis & Optimization Digital System , Advance Topics Semiconductor Devices, Adv Spec Top in EE,VLSI, Wireless Communication, Intelligent Control Systems

References Available On Request

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