Resume_Product_Engineer

Harish Sankaranarayanan

*** ******* ** #****, *******, TX 75019

Phone: 972-***-**** (Home), 214-***-****(Cell)

Email: ******.****************@*****.***

OBJECTIVE

Pursue a challenging career that utilizes my experience in Device Engineering, EWS Yield Enhancement, Process Integration, Process Development, Technology/Product Transfer, Device Processing, and Characterization of Semiconductor Devices and Technologies.

EDUCATION

•Doctorate (Ph.D.) in Microelectronics, Electrical Engineering, University of South Florida, Tampa, Florida (May 98 – Aug 04) GPA:3.93/4.0.

Dissertation: Fabrication of CIGS Solar Cells by a Manufacturing-friendly Two-Stage Process.

•Master of Science (M.S.E.E) in Microelectronics, Electrical Engineering, University of South Florida, Tampa, Florida. (Jan 96 – Apr 98). GPA:3.89/4.0.

Thesis: Effective Processing Conditions for CIGS Thin Film Solar Cells using a Top Cu layer.

•Bachelors of Engineering (B.E) in Electronics and Communication Engineering, University of Madras, Chennai, India. (Aug 91 – May 95).

SKILLS

•Strong Knowledge of PN Diodes, CMOS, BJT and DMOS Device Physics and Characteristics.

•Hands on Experience in EWS Yield Enhancement of Mixed-Signal ICs.

•Strong Knowledge of BICMOS and BCD Process flows and Integration.

•BICMOS Process Transfer and Process Development.

•Expertise in Statistical Data Analysis (Six Sigma) Tools and Problem Solving.

•Project Management, Crisis Management and Risk Assessment.

•Interfacing with Multiple Groups to Resolve Integration/Yield Issues.

•Excellent Oral and Written Communication Skills.

WORK EXPERIENCE

Senior Device Engineer (8/04 – present)

ST Microelectronics, Carrollton, Texas.

•Electrical Wafer Sort Yield Enhancement & Low Yield Analysis of Mixed Signal ICs.

•Process Integration and Technology/Process Transfer of CMOS, BICMOS and BCD Products.

•Process Transfer Lead for transfer of BICMOS Technology as well as MOS Based Printhead Technologies.

•Investigation of Parametric Failure/Drift of electrical components using tools like Machine Commonality/Timeline, Correlations, Parametric comparison (TPFP), Physical and Electrical Bench Test using HP4156A

•Perform Correlation Analysis between electrical parameters and EWS bins/tests or inline process parameters to identify root cause of Yield loss or parametric shift.

•Parametric Statistical Process Control (SPC) project Coordinator – Successfully implemented recipes using KLA ACEXP on several technologies to monitor parametric drifts.

•Parametric CPK analysis & improvement to ensure process repeatability and stability.

•Part of team that implemented special inking schemes like PPAT, GPAT and SPAT to achieve 0ppm requirement for Automotive products.

•Interfacing with Process, Product and Design engineers to communicate and resolve problems affecting electrical parameters and EWS yield in a timely manner.

•Process flow/Route setup for qualification of new IC products.

•Create and Review Technology FMEA and Control Plan.

•Disposition of Non-Conforming (NCL) and Special work request (SWR) lots to ensure Quality & Reliability.

•Material Review Board (MRB) Disposition of Automotive Products Failing EWS Statistical Bin Limit (SBL).

•Support Quality group on Customer returns – involves root cause analysis and exchange of sensitive information.

PROJECTS

Parametric SPC Project Coordinator

•Implemented Parametric SPC on Schedule on all major Technologies in Production using KLA ACEXP.

•Several cases of process drifts were identified early preventing major excursions and greatly reducing potential scrap.

•Tester issues were also detected – alignment/calibration of testers led to reduction of false alarms.

Process Transfer of BiCMOS Technology

•Process Integration Engineer/Process transfer team Coordinator for Sending plant.

•Met Timeline on all deliverables while adhering strictly to company process transfer guidelines.

•Provided Technical support in a timely manner for solving issues encountered by the receiving plant.

GPAT Yield Loss Reduction on BCD Automotive Products

•Interfaced with Product engineers to fine tune GPAT recipe.

•Optimal Cluster size and cluster thresholds were achieved after several iterations.

•Quality was ensured for Automotive grade products while minimizing yield loss – Yield Enhanced 1.5%

EWS Yield Enhancement on BCD Audio Amplifier Product

•Identified design marginality of EWS Low Gain Test to PLDMOS Vt and NPN gain through correlation analysis.

•Split lots were run to confirm correlation results.

•Process Change was implemented to reduce PLDMOS Vt to Prevent yield loss. EWS Yield gain 5%.

Process Integration/Transfer for Printer Chip

•Integration Engineer responsible for Process Flow setup to match R&D plant.

•Optimized SOG Etchback and Metal deposition processes to improve via filling.

•Parametric analysis of pathfinder lots.

•Excellent EWS yields were achieved on Qual lots.

ACADEMIC WORK EXPERIENCE

Research Assistant (1/96 – 8/04)

Dept. of Electrical Engineering, Thin Film Semiconductor Laboratory, University of South Florida, Tampa, Florida

•Extensive Experience in Efficiency Improvement of CIGS/CdS Thin-Film Solar Cells fabricated by a Two-Stage sequential Physical Vapor (PVD) deposition process.

•A comprehensive study of the Glass/Mo/CIGS/CdS/ZnO structure.

•Expertise in Sputtering (DC & RF), Evaporation and Chemical Bath Deposition (CBD).

•Design of Experiments.

•Device modeling and failure analysis.

•Characterization of Thin-Film solar cells using I-V (HP 4145B), C-V (HP4194A) and QE Measurements.

•Characterization of films using Four-point probe, Transmission/Absorption Spectroscopy & Profilometry

•Extensive Experience in Design, Assembly and Maintenance of Vacuum Systems & Leak Detection.

HONORS, AWARDS & CERTIFICATIONS

•2008 Achievement Award: In Recognition of Outstanding Performance in Implementation of Parametric SPC.

•2007 Achievement Award: In Recognition of Outstanding Performance in Yield Improvement.

•Member: Eta Kappa Nu, an Electrical Engineering Honor Society.

•Six Sigma Green Belt Certified.

COMPUTER SKILLS

•EDA CAD Tools: MAGIC, ESPRESSO, ESIM, KLA ACE XP, PROWAY, SAS, MINITAB.

•Languages & Packages: C, PASCAL, and FORTRAN 77. MathCAD, MS Office Suite, Lotus 123.

•OS: WINDOWS, MS-DOS, UNIX, SOLARIS.

WORK STATUS: Permanent US Resident (Green Card).

PUBLICATIONS

•V. Mohanakrishnaswamy, H.Sankaranarayanan, C. S. Ferekides, D. L. Morel “ The Effect of Mo Deposition Conditions on Defect Formation and Device Performance for CIGS Solar Cells” Proceedings of the 31st IEEE Photovoltaic Specialist Conference, January 2005.

•H.Sankaranarayanan, V. Mohanakrishnaswamy, C. S. Ferekides, D. L. Morel “ The Influence of Impurities on Growth and Properties of CuIn1-xGaxSe2 using Two-Step Processing” European Materials Research Society Meeting, June 2004, Strasbourg.

•P. Panse, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Ga Incorporation Mechanisms in CIGS Solar Cells,” NREL Review Meeting, April 2000, Colorado Springs, CO

•P. Panse, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Evaluation And Modeling of Junction Parameters in Cu(In,Ga)Se2 Solar Cells,” Proceedings of the 28th IEEE Photovoltaic Specialist Conference, Sept 2000, Anchorage, AK

•M. Shankaradas, Y. Ying, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Photocapacitance Analysis of Defect Mechanisms in Cu(In,Ga)Se2 Solar Cells,” Proceedings of the 28th IEEE Photovoltaic Specialist Conference, Sept 2000, Anchorage, AK

•A. Jayapalan, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Interface Mechanisms in CIGS Solar Cells,” NCPV Program Review Meeting, September 1998, Denver, CO

•A. Jayapalan, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Determination of Fundamental Parameters And Mechanisms in CIGS Solar Cells Using PhotoCapacitance Techniques,” Proceedings of the Second World PV Conference, July 1998, Vienna

•R. Narayanaswamy, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Achievements of High Jsc’s in ZnO/CIGS Heterojunctions Using Reactively Sputtered ZnO,” Proceedings of the Second World PV Conference, July 1998, Vienna

•R. Bhatt, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “The Dependence of Reactively Sputtered ZnO Electronic Properties on Growth Parameters for Use as Buffer Layer in CuInxGa1-xSe2 Solar Cells,” Proceedings of the 26th IEEE Photovoltaic Specialist Conference, 1997, Anaheim, CA

•S. Zafar, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “The Use of Ga in Two-Step Processing to Optimize the Electronic Properties of CuInxGa1-xSe2 Solar Cells,” Proceedings of the 26th IEEE Photovoltaic Specialist Conference, 1997, Anaheim, CA

•S. Zafar, J. D’Amico, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “The Effect of Surface Processing Conditions on the Junction Properties of CuInxGa1-xSe2 Solar Cells,” Proceedings of the 14th NREL/SNL Photovoltaics Program Review, November 1996, Denver.

•S. Zafar, J. D’Amico, H. Sankaranarayanan, C. S. Ferekides, D. L. Morel, “Processing And Characterization of I-III-VI2 Compound Semiconductor Solar Cells,” 24th Annual Symposium, AVS, February 1996, Orlando, FL.

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