Design Assistant

Curriculum Vitae

ALEX MITEV

- **** W Ironwood Hill Dr. Apr 14269, Tucson, AZ 85745

- Phone: 520-***-****, 520-***-****

- E-mail: *****.****@*****.***,

INTERESTS

Summary

- Strong interest and theoretical background in the area of Electronic Design Automation (EDA), including circuit simulations, design for manufacturability (DFM), timing analysis, device macromodeling, characterization and device physics.

- Experience in soft-error mitigation techniques of circuits in irradiative environment. Researched new methods for circuit robustness estimation. Research interest in methods for circuit radiation hardening.

- Experience and scientific interest in compact models, and process variation modeling. Research in developing models that accurately capture the circuit performance statistics due to manufacturing variability.

- Experience with several Model Order Reduction (MOR) techniques, in applications of timing analysis. Research work and publications in inversed regression methods.

- Practical experience with linear and nonlinear optimization, numerical methods for approximation and system identification. Research work in area of soft computing, including neural network applications for system identification and pattern analysis, statistical learning such as support vector machine, and evolutionary algorithms. Interest in knowledge engineering and computational intelligence.

EDUCATION

2009-Ph.D.

University of Arizona, Tucson, USA

- Major in Electrical Engineering., Minor in Systems and Industrial Engineering

- Dissertation topic: "The new VLSI technology challenges in nanometer design scale - the impact of the high system integrity and process variations"

2000-Ph.D. unfinished

Institute Informational Technologies, Sofia, Bulgaria

(Transferred to UA in 2002)

- Major in Computer Engineering.

- Accomplished course work and passed the qualify exam.

- Dissertation topic: "Neural networks with application to system identification and pattern recognition"

1996-M.S.

Technical University of Sofia, Sofia, Bulgaria

- Major in Electrical Engineering.

- Master's thesis: "68020 based versatile microprocessor controller"

1993-B.S.

Technical University of Sofia, Sofia, Bulgaria

- Major in Electrical Engineering.

WORK EXPERIENCE

2011

Embedded System Developer-"Strongwatch" LLC, Tucson, AZ (contract position)

- Worked as an embedded system developer (C++, Python, Matlab, RTOS, Linux)

- Improved the geo-positioning features of "Freedom"-a multi-sensor surveillance system.

- This position requires an experience with various sensor modules and interface buses.

2009-2010

Senior Researcher-Siera LLC, Tucson, AZ (part time position)

- Research in the area of Soft Error impact on digital ICs-circuit robustness estimation due to single and multiple events upsets, soft-error mitigation techniques, and radiation hardening mechanisms for processor cores.

- Developed a tool for circuit robustness estimation. Demonstrated two fold of performance improvement for large scale of circuit design, as compared to related estimation tools.

- Contributed several proposals for DoD, DoE, and NASA.

2006-2009

Research Assistant-Digital VLSI Design Lab - ECE, University of Arizona

- Research topic: "Nanoscale silicon devices-process variations and macromodels".

- Developed an advanced compact gate model (AND, OR, INV) for accurate estimation of the performance metrics, such as the gate intrinsic delay and power dissipation. The model is built upon several distinct points on I-V gate curves (Finite Point (FP) model).

- Implemented a workflow for studying the proposed model, and extended the variable space to include the transistor manufacturing variability, such as deviation at the transistor geometry (LEFF, WEFF, TOX) and threshold voltage mismatch (VTH).

- Improved the proposed model to capture the leakage power, and extended the workflow for sequential circuits by modeling D flip-flop. Calibration of the FP model, based on comparing HSPICE simulation results and experimental I-V data.

- This position requires programming skills in Verilog-A, Python, Matlab and C++.

2008

Research Assistant-SIE, University of Arizona

- Worked on a project of Stochastic Linear Programming, and implemented a novel algorithm for finding the robust solution. The proposed method solves a random linear problem by given rating of the optimality and uncertainty of the solution.

- Used industry package COIN-OR (C++) and Matlab.

2004-2006

Research Assistant-Digital VLSI Design Lab - ECE, University of Arizona

- Research topic: "Model Order Reduction (MOR) and methods of estimation the circuit performance metrics".

- Developed new process variation aware MOR method, for application of circuit performance function (PF) estimation, such as timing. Demonstrated better reduction in comparison to PCA-based approaches.

- Implemented two distinct methods: Sliced Inverse Regression method, which requires parameter sampling to formulate the regression model of the PF, and Principle Hessian Directions (PHD) method, which by given PF analytical expression, reduces the parameter space by means of pruning statistical insignificant directions.

- Improved the gate timing modeling by using Probabilistic Collocation Methods and arbitrary process variation distribution. Calibration and justification the final model with competitive Monte Carlo simulations from HSPICE simulations. Implemented a tool for fast timing characterization in C and Matlab

2003-2004

Research Assistant-Cancer Center, University of Arizona

- Worked in a Bioinformatics lab on project of novel drug discovery for pancreatic cancer.

- Responsible for the analysis of microarray genome data. Implemented algorithms for pattern recognition, and statistical modeling .

- This position requires experience in GA, machine learning, and VBA programming.

1997-2000

Research Assistant-Institute Information Technologies, Sofia , Bulgaria

- Developed neural network applications for pattern recognition and system identification (Matlab, C). Coauthored on three scientific papers.

COURSE WORK

Graduate level courses

- Device Electronics, Computer Aided Logic Design, Analog Integrated Circuits, Advanced Logic Synthesis. Algorithms and Verification, Digital VLSI System Design, Random Processes in Engineering Application, Stochastic Processes, Fundamentals of Optimization Theory, Introduction of Machine Learning, Knowledge System Engineering, Engineering Application of Graph Theory, Data Structures and Algorithms, Data Base Management, Decision Making Under Uncertainty, Electronic Devices and Circuits, Computer System and Networks, Fundamentals of Computer Architecture Parallel Computer Systems, Linear Systems.

Undergraduate level courses

- Physics I, Physics II (including Basic of Solid State Physics, and Semiconductor Physics).

Computer skills

-

- Programming languages: Matlab, C, C++, Python, Perl, VBA, VB.

- Engineering tools: Cadence Spectre, Berkley Spice, HSPICE, Verilog, Verilog-A, VHDL.

PUBLICATIONS

JOURNAL ARTICLES

- O. Hafiz, A. Mitev, and J.M. Wang, "A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty," The Institute of Electronics, Information and Communication Engineers, Vol. 92A, No. 4 (March 2009), pp. 1148-1160.

- J.M. Wang, Y. Cao, C. Min, J. Sun, and A. Mitev, "Capturing device mismatch in analog and mixed-signal designs," IEEE Circuits and Systems Magazine, Vol. 8, No. 4, 2008, pp. 37-44 (Invited paper)

- A. Mitev, M. Marefat, D. Ma and J.M. Wang, "Principle Hessian Direction Based Parameter Reduction with Process Variation," IEEE Transactions on VLSI Systems, 2008 (accepted for publication).

- A. Mitev, M. Marefat, D. Ma and J.M. Wang, "Parameter Reduction for Variability Analysis by SIR Method," IEE Proceedings for Circuits, Devices and Systems, IET Circuits, Devices & Systems, Vol. 2, No. 1 (February 2008), p. 16-22

CONFERENCE PAPERS

- D. Ganesan, A. Mitev, J.M. Wang, and Y. Cao, "Finite-point gate model for fast timing and power analysis," 9th International Symposium on Quality Electronic Design (ISQED'08), 2008, pp. 657-662.

- A. Mitev, M. Marefat, D. Ma, and J.M. Wang, "Principle Hessian Direction Based Parameter Reduction with Process Variation", International Conference on Computer-Aided Design (ICCAD'07), 2007, pp. 632-637, Best Paper Award Nomination.

- A. Mitev, M. Marefat, D. Ma, and J.M. Wang, "Principle hessian direction based parameter reduction for interconnect networks with process variation." System Level Interconnect Prediction (SLIP'07), 2007, pp. 41-46.

- A. Mitev, D. Ganesan, D. Shammgasundaram, Y. Cao, and J.M. Wang, "A Robust Finite-Point Based Gate Model Considering Process Variations", International Conference on Computer-Aided Design (ICCAD'07), 2007, pp. 692-697.

- A. Mitev, M. Marefat, D. Ma, and J.M. Wang, "Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method", Asia and South Pacific Design Automation Conference (ASPDAC'07), 2007, pp. 468-473.

- V. Agarwal, J. Sun, A. Mitev, and J.M. Wang, "Delay Uncertainty Reduction by Interconnect and Gate Splitting", Asia and South Pacific Design Automation Conference (ASPDAC'07), pp. 690-695.

- J.M. Wang, A. Mitev, and N. Kankani, "Collocation Method based RC/RLC Extraction with Process Variation", Progress in Electromagnetic Research Symposium (PIERS'05), 2005,Hangzhou China.

HONORS AND AWARDS

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- The 11th Annual ACM SIGDA Ph.D. Forum/Member Meeting at Design Automation Conference, DAC-2008, Acceptance rate 30%

- Richard Newton Graduate Scholarships Award with Adviser: J. Wang, Design Automation Conference, DAC-2008

- Nominated for Best Paper Award at the International Conference for Computer-Aided Design ( ICCAD'07 ) 2007

PROFESSIONAL EXPERIENCE

REVIEWER FOR

- Journal of Electronic Testing

- Annals of Mathematics and Artificial Intelligence

- Journal of Universal Computer Science

- Various conferences including: ASPDAC, ASQED, ISQED, ISCAS, etc.

REFERENCES

References available upon request

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