Hardware Engineer

Rashmi Joshi

*** ********* ******, *** # *, Voice: 650-***-****

Foster City, CA 94404 Email: ******.********@*****.***

USA VISA: Permanent Resident

SKILLS SUMMARY

Ø Three plus years of experience with complex ASIC/FPGA design and verification

Ø Knowledge of custom ASIC design flow

Ø Extensive experience in Verilog and VHDL RTL coding, simulation and logic synthesis

Ø Working experience with ModelSim, Cadence’s NC Verilog, VCS Leapfrog for simulation

Ø Working experience with Synopsys Design Compiler, Synplicity for FPGA synthesis, Formality for functional verification, timing designer, SPICE, SignalScan, Undertow, CVS and VSS for version control

Ø Knowledge of IEEE 802.3, packet over SONET(OC192), communication protocols TCP/IP, UDP etc

Ø Familiarity with PCI bus architecture, AMBA AHB architecture and 1394A bus architecture

Ø Familiar with computer architecture

Ø Knowledge of basic PERL scripting for test data generation

Ø Basic knowledge of MATLAB

INDUSTRY EXPERIENCE

Ø Intern, Atmel Corporation, San Jose, California Aug 2006 – Dec 2006

Testing of new fitter (s/w written to test the PLD) version for ATF15xx series of PLDs.

New fitter versions are tested using okay chips using various test cases.

· Used existing test cases to test the new fitter version which enabled them to test new PLDs.

· Designed new test cases verilog/vhdl for the same to cover more testing for the PLDs.

· Tested the new fitter for all packages of ATF1502/04/08 and documented all the results. This served as a foundation for the new person handling the PLD testing.

· Used various tools: Prochip 4.0, wincupl (Atmel), ISP 6.1 , Modelsim(Mentor), Maxplus II (Altera).

Ø VLSI Design Engineer, Wipro Technologies, Pune, India Jan 2001 – May 2003

(1) Conversion and porting of a DSP core

The project was to convert the DSP core written in M-language to VHDL and improving on Power, Performance and Area. Because of good performance was assigned the quality reviewing for the project.

· Owned about one seventh of the part of the core and performed the following:

· Conversion of the M-language code to VHDL, formal verification (Formality) for functionality.

· Simulations on the client provided test case suites and synthesis.

· Design changes for power, performance and area improvement.

(2) Titan FPGA for AVID

Titan FPGA serves as a memory, stream controller, and interface between pipeline segments, host bus, etc.

Joined the team halfway and showed excellent understanding of the project doing the following:

· Design and implementation (VHDL) of run length encoding decoder for client specifications

· Preparation of test cases for edit display resizer and run length-encoding decoder.

· PERL scripting for test data generation and comparing actual results with ideal for EDR testing.

(3) Implementation of Giga bit Ethernet PCS (Was used to test MAC layers in the IP development group)

· Responsible for RTL coding (Verilog), testing and synthesis of GE(IEEE 802.3) PCS transmitter.

· Design of 8b/10b encoder and generation of special code groups for on the signals on the MAC interface.

· Involved in the integration of all the sub-modules and testing the integrated PCS core.

(4) Packet over SONET test bench forOC192 test equipment(Was successfully used for actual testing onsite)

· VHDL implementation of a packet over SONET receiver and integration and the testing of the sub-modules.

· Handled project bug tracking for shipping a bug-free product.

(5) AMBA AHB models (These were used by the IP verification group)

· Study of AMBA AHB bus architecture.

· RTL (Verilog) implementation of AHB master.

· Involved in final integration.

Ø Project Trainee Engineer, ControlNet India Pvt. Ltd., Goa, India May 2000 – Nov 2000

Project: Verification of the 1394 a, 8 port switch

· Study of 1394-a standard. Developed a protocol monitor for the PHY-link interface of the 1394-a standard.

· This module was used to debug the open host controller interface (OHCI) link layer controller (LLC) model

RECENT PROJECTS

· MS final project: PCI-Express Bridge for Multi-Processor Environment Aug 2007 – Dec 2007

Implemented transaction layer of a PCI Express compatible device. The device is basically two back to back connected PCI-express devices acting as a bridge between processor memories, hence the name. It was coded in Verilog, simulated in Modelsim and synthesized. It meets required frequency (2.5 GHz/32 bit ~ 80 MHz).

· CMOS Digital Circuits: 4-bit CMOS Decimation filter using SPICE Aug 2005 – Dec 2005

A 4-bit decimation filter was designed using SPICE in 0.5-micron technology. The decimation factor was 4. The circuit was laid out and extracted and passed LVS. Cadence tools were used for the same.

· Advanced Logic Design: A 32-bit Carry Look Ahead Subtractor using Verilog.

A 32-bit Synchronous and Asynchronous CLA subtractor was designed and implemented in Verilog. It was synthesized in dc_shell.

· Digital System Design and Synthesis: Low-pass FIR filter Design Aug 2005 – Dec 2005

A low-pass FIR filter with order of 10 and cut-off frequency of 14.8 MHz was designed for video application. The filter coefficients were found using MATLAB, RTL coding was done in Verilog, simulations on Modelsim, and synthesis in Design Analyzer.

· ASIC CMOS Design: Simple network switch Feb 2005 – May 2005

A simple network switch handling TCP/IP protocol was designed and implemented in Verilog

COMPUTER SKILLS

Hardware Description Languages: Verilog, VHDL

Programming Languages: Knowlwdge of C, 8085 Assembly language

Operating systems: Windows, Unix

EDUCATION

· Masters in Electrical Engineering, (Jan 2005 - Dec. 2007), GPA: 3.63

Major: Logic/Digital system and ASIC/VLSI Circuit Design

San Jose State University, CA

· Diploma in VLSI Design (Nov 1999 – Apr 2000), GPA: 3.5

C-DAC Nagpur, India

· Bachelor of Engineering (Aug 1994 – Jun 1998), GPA: 3.7

Electronics and Telecommunications, Government College of Engineering, Aurangabad, India

PAST ACADEMIC PROJECTS

· Design of PCI compatible Master and Bus Arbiter

A PCI compatible master device and a PCI bus arbiter was designed for the bus width of 32 bits and clock frequency 33 MHz. The RTL coding was done in VHDL.

· Microprocessor to microprocessor wireless communication

Intel’s 8085 were programmed using assembly language. The 8251 USART was used as the communication interface. The project included, design of fm modem, design and fabrication of the FSK modem and programming the 8085.

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