Electrical Engineer

Mathias Gene Hotaling

*******@****.***.***

** ********* ******

South Burlington, VT 05403

Cell Phone 802-***-****

Objective

To obtain a leadership position to challenge myself professionally and expand my knowledge and skills.

Work Experience

Circuit Design Engineer 9/2006 – 12/2008 ASIC North, South Burlington, VT

LVDS IO Conversion/Design and Verification for 65nm and 45nm technology.

Full LVDS Stability and Reliability Analysis for Process Variation Considerations.

Test Site Design and verification for 180nm and 65nm Technology advancement.

Design Data Transfer from node to node and tool to tool.

Foundry Design & Characterization Engineer 4/2004 – 8/2006 IBM, Burlington, VT

Test Site Design and Verification for 120nm, 90nm, and 65nm technology advancement.

Model-to-Hardware Correlation and Data Analysis for experimental ASIC/Foundry Testsites.

Device Model evaluation for enhancement of IBM ASIC/Foundry Technology Library.

Extensive circuit documentation for development of Test Team measurement procedures.

DRAM R&D Product Engineer 9/2002 - 2/2003 Micron Technology Boise, ID

Maintained product inventory through production and front-end testing for development team.

Failure characterization on experimental DRAM devices at the bare die and packaged-part stages.

Analyzed post-stress test data to identify links between production errors and final product failure.

Advanced ASIC Design Engineer 1/2000 - 8/2000 IBM Microelectronics, Burlington, VT

Developed cells and peripheral logic parts for an ASIC Content Addressable Memory (CAM).

Met with Design Engineers and Patent Attorneys to protect newly developed technology.

Prepared descriptive technical documents for patent application.

Education

Rensselaer Polytechnic Institute 1997-2002, Troy, NY Bachelor of Science, Electrical Engineering

Work and Computer Skills

VLSI Design, Layout and Verification: Cadence, Tanner Tools, Cadence-to-Tanner-to-Cadence Conversion, Gym, LVS and DRC using Hurcules & Calibre, Layout Extracted simulation using IBM Model Libraries.

Integrated Circuit Test: Working knowledge of wafer and packaged-part level test hardware and procedures. Created Specification and Test Methodology documentation for test team. Assisted in debug of test automation implementation.

Other: Semiconductor device physics, familiarity with manufacturing process. UNIX, VHDL, Verilog, Synopsys, Perl, C, C++, HTML, Lotus Notes, MS Office, Mat lab

Related Classes

Fields and Waves, Physical Design of Microelectronics, VLSI Design, Engineering Economics and Project

Management, Microelectronics Technology, Digital Electronics, Analog Electronics, Signals and Systems,

Electric Circuits, Laboratory Introduction to Embedded Control

Leadership

Peer Tutor for Analog & Digital Electronics, 8/01-12/01 Rensselaer Learning Center Troy, NY

Physics Teaching Assistant, 8/99-12/99, 8/00-12/00 Rensselaer Physics Department Troy, NY

Student Orientation Advisor, Summer 1999 Rensselaer Polytechnic Institute Troy, NY

Rensselaer ECSE Peer Advisor, Summer 2000 Rensselaer Polytechnic Institute Troy, NY

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