Electrical Engineer with experience in Analog Mixed signal circuit design and Power electronic circuit design seeking a fulltime opportunity in the field of Analog/Digital circuit design

Areas of Focus Include PLL, CDR, Data Converters, Dc-Dc converters

PROFESSIONAL WORK EXPERIENCE:

Arasan Chips Systems San Jose, CA Sep 2010 - Current

Analog Design Intern

• Circuit design of analog transceiver IP’s for Mobile Industry Processor Interface ( MIPI) protocol

• Designed a bandgap reference with 1.2V supply in IBM 65nm

• Designed a voltage - current converter to generate currents for PLL blocks in IBM 65nm

• Worked on schematic design and layout of PLL digital and analog blocks in TSMC 130nm and IBM 65nm

mPowerSolar San Jose, CA Jan 2010 – Aug 2010

Analog Design Intern

• Design of a Microinverter that attaches to the racking beneath a solar module and converts DC power to grid-compliant AC power

• Designed and tested DC-DC (Push Pull & Half Bridge Resonant) converters and DC-AC (Hex Bridge) 300W 3-Phase Inverter circuits

• Designed automation test benches to test Inverter PCBs in LabVIEW Data Acquisition System

• Performed Matlab, LTSpice & PSIM simulations as well as PCB prototyping

• Conducted soldering and testing using Tektronix 500Mhz- 2 GS/sec oscilloscope.

EDUCATION

Electronic Circuits (Certification Courses) (Current)

Stanford University Stanford, CA

Master of Science in Electrical Engineering (Dec 2009)

San Jose State University San Jose, CA

• J. D. Patil, L. He and M. Jones, “Clock and Data Recovery for a 6 Gbps SerDes Receiver”

Bachelor of Science in Electrical Engineering (Jun 2006)

University of Mumbai Mumbai, India

TECHNICAL SKILLS SUMMARY:

EDA Tools: Cadence Virtuoso Spectre, Mentor Graphics Calibre, Synopsys VCS, Design Analyzer, Synopsys Sentaurus, Xilinx ModelSim, LTSpice, PSIM, MATLAB

HDL: Verilog HDL, Verilog AMS

Languages: C, Perl, SKILL, HTML

Lab Tools: LabVIEW , Oscilloscope, Multimeter, Soldering

Operating Systems: UNIX, Linux, MS Windows

ACADEMIC PROJECTS:

MS Project: Clock and Data Recovery Circuit for 6Gbps SerDes in CMOS 0.13um:

• Designed a differential analog front-end comparator and dual loop PLL

• Verilog AMS Modeling in Synopsys VCS, Schematic and Layout implementation in CMOS 130nm technology.

Regulated cascode TIA in 0.18um SiGe BiCMOS process ( EE214: Stanford):

• Design of a transimpedance amplifier in Hspice using SiGe 0.18um Technology

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