Amudhan.D/M.E(VLSI Design)/8.29 CGPA/Anna university/trainee engineer

AMUDHAN.D

Master of Engineering in VLSI Design

E-mail: *********@*****.***

Mobile: +91-812*******

Objective:

To pursue a challenging and exciting career in the field of VLSI, thereby acquiring knowledge and work towards organizational and personal growth. Enthusiastic about learning and developing Professional Skills in a growth oriented environment.

Academic Credentials:

• M.E [VLSI Design] from Anna University Coimbatore in 2010 with 8.29 CGPA.

• B.E [Electronics & Communication Engineering] from Kings College of Engineering (Anna University Chennai) in 2007 with an aggregate of 64%.

• HSC, Laurel Higher Secondary School in 2003 with 64%.

• SSLC, R.K.M.S.V. Matriculation School in 2001 with 65%.

Skill Set:

Programming Languages : C, C++ (Intermediate).

HW Description Languages : Verilog.

HVL : System Verilog.

EDA Tool : ModelSim, Microwind, Tanner, Xilinx9.2i,

Altera (QuartusII).

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, Simulation, FSM based design, Code Coverage,

Functional Coverage, Synthesis, Static Timing Analysis.

Experience

• One year experience as VLSI Trainee Engineer in ARMADA INDUSTRIAL AUTOMATION from July 2010 to August 2011.

• Accompanied with Maven Silicon, VLSI Design and Training Center as Design/verification Engineer from November 2011 – Till date

Trainings:

• Certified course on “Advanced VLSI Design & Verification” at Maven Silicon VLSI Design & Training Centre, Bangalore

• Certified Course on C, C++ and HTML at CSE.

Excellency:

• “Architectures to reduce latency and complexity for Viterbi Decoder” paper presented in the national level conference NCSCV ’10 held at Anna University Coimbatore.

• “Mentor Graphics Based VLSI Design Flow” participated in the one day national workshop at Anna University Coimbatore.

• Worked as Coordinator for “National Level Technical Symposium” conducted at Anna University Coimbatore.

• Attended international conference “User2User India 2009” organized by mentor graphics held at Bangalore.

• Attended One Day National level work shop “Microwind Tool” (Layout Design), Technology: 30nm, 45nm conducted at Anna University Coimbatore.

Projects:

SPI Controller Core - RTL Design

HVL: Verilog.

EDA Tools: Xilinx, Questa -- Verification Platform.

Description : The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock.This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register.The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification sign-off.

Real Time Clock – RTL design and verification

HDL: Verilog.

HVL: SystemVerilog..

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Real Time Clock using Verilog HDL independently.

Architected the class based verification environment using SystemVerilog.

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design .

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently.

Architected the class based verification environment using system Verilog.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification sign-off.

Architectures to Reduce Latency and Complexity for Viterbi Decoders

PLATFORM : Architecture in Communication System.

TECHNOLOGY : 180nm.

LANGUAGE USED : Verilog.

TOOLS : Modelsim 5.7, Xilinx 9.2.

ROLE : Low Power and Reduce Latency and complexity.

DESCRIPTION : Viterbi Decoder is commonly used in decoding convolution codes for wireless communication.In Viterbi Decoder look-ahead techniques for achieving high throughput. Look ahead level increases- complexity and latency decreases. There are 3 major building blocks.BMU (branch metric Unit),ACS (add-compare-select Unit),Survival Memory Unit(SMU).Multiple steps of trellis to single step (complex) using Branch Metric Precomputation (BMP).The Branch Metric Precomputation dominate complexity and latency of the architecture. Reduce complexity, latency and increases the frequency speed of the decoder.

Extra Curricular Activities:

• Undergone In plant Training in “BSNL”- Thanjavur & “All India Radio”- Trichy during my undergraduate.

Personal Memorandum

Father’s Name : Datchinamoorthy K.

Mother’s name : Mullai Ammal.S

Date of Birth : 26-09-1985.

Permanent Address : 26/6, Adhi street, Pattukkottai,

Thanjavur Dist, Tamil Nadu, Pin Code -614601.

Present Address : no: 4, Gowrishankar Complex,

Arekere Gate, Bannarghatta Road,

Banglore-560076.

DECLARATION

I here by declare that the above mentioned information is true to the best of my knowledge and belief.

(AMUDHAN .D)

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