Ron Feldman
Campbell, CA *****
***@****.***
http://www.linkedin.com/in/ronfeldmanengineer
Engineering position involving manufacturing, quality/reliability, technical writing and/or the resolution of high-visibility customer issues
Quality Assurance involving risk reduction, manufacturing, RMA corrective actions, ISO9000 conformance (Certified ISO9000 Internal Auditor; Handley-Walker) and QS9000/TS16949/AIAG automotive market segments with Advanced Product Quality Planning (APQP). All issues subject to 8D & FMEA analysis resulting in both immediate and permanent corrective actions. Over 15 years of successful resolution of automotive customer RMA issues; hands-on failure analysis, inventory containment, documentation and permanent corrective actions.
Reliability & Failure Analysis to deprocess and analyze integrated circuits using microprobe, liquid crystal, SEM, FIB, EDX, package X-Ray, SAM and other techniques. Silicon/package qualifications per MIL-STD-883, AEC-Q100 and JEDEC specifications; burn-in, thermal cycling, biased temperature-humidity bake, 85/85, autoclave, ESD, HALT/HAST and latch-up, as well as application-specific stresses; extensive burn-in hardware design.
Product/Test Engineering on analog, high-voltage DMOS, CMOS non-volatile memory and mixed-signal products involving characterization, test, qualification, failure analysis, statistical yield & parameter analysis and ongoing yield enhancement. Test program generation for characterization, production and reliability testing as well as offshore assembly/test subcontractor interface.
Component Engineering & Supply Chain Management involving component selection, qualification, scheduling & process changes, as well as ISO9000 survey audits, RMA activity and corrective actions. RoHS and WEEE qualification of lead-free semiconductor products based on JEDEC requirements and existing subcontractor data, as well as other ‘green’ environmental specifications.
Technical Writing on semiconductor datasheets, application notes, reliability reports, automotive qualification packages and ISO9000-compliant documents and processes.
BSEE, University of New Mexico, Albuquerque, NM
Statistical Process Control (Level 3), National Semiconductor
PROFESSIONAL HISTORY:
Member – IEEE, ASQ (American Society for Quality)
Owner, Budget Blinds of Los Gatos, Campbell, CA
2008 - 2011
Sales, QuickBooks accounting and resolution of customer issues. Leads developed from internet & local advertising with sales of $17,000/month.
Partner, Yellow Cottage Mosaics (Art Sideline), Campbell, CA
2005 - Present
Custom mosaic art - Business development & QuickBooks accounting.
* Installed artwork for Santana Row shopping center, city of Campbell and Garden Tour of Los Gatos.
Quality Assurance Engineer, Integrated Circuit Systems, San Jose, CA
2003 - 2005
CMOS clock products - Failure analysis of field failures using ATE, bench-test & f/a labs with 8D analysis, root cause definition and corrective actions. Served as ISO9000 team leader/auditor and responsible for documents in conformance to ISO9000.
* Responsible for failure analysis and all RMA activity; primarily Japanese & European markets, successfully resolved all issues within customer’s expected timeframe.
* Multiple supplier qualifications of package families to lead-free, ‘green’ RoHS/WEEE standards resulting in uninterrupted product deliveries during ‘green’ package conversion.
* Resolution of lead-free TSSOP package die-paddle delamination issues with assembly subcontractors allowing assembly of product in ‘green’ TSSOP package families.
* Successful completion of ISO9000 audits for San Jose facility; documentation & conformance.
Technical Writer (Contract), OmniVision Technologies, Sunnyvale, CA
2002
CMOS camera-chip products - Technical writing for datasheets/application notes using FrameMaker.
Component Engineer, LTX, San Jose, CA
2001 - 2002
Mixed-signal ECL hybrid products - High-speed ATE test & characterization, manufacturing support on assembly process and engineering for BOM/BOR changes. This involved failure analysis of test rejects and corrective actions with manufacturing locations.
* Reduced inventory test backlog 40% allowing disposition & recovery of aged/damaged product.
* 24-hour typical ECO turnaround time decreasing overhead for product/process changes.
* Member, Philips PSK Reliability team, resolved PECHF failures on Fusion tester line
Reliability & Quality Assurance Engineer, Veridicom, Santa Clara, CA
2000 - 2001
CMOS fingerprint sensors - Qualification and failure analysis of large-die silicon fingerprint sensors and customer RMA returns. Generated 8D reports, defined root cause and executed immediate/long-term corrective actions. Bench & ATE reliability testing and continuous improvement of quality/reliability targets as well as ISO9000 audits and facility compliance. Also responsible for supply chain management of assembly parts, services and RMA quality issues.
* Qualification of product line ($7M P/L) involving initial & revised silicon releases. Consistently exceeded aggressive scheduling, finishing reliability processing on-time and within budget resulting in uninterrupted delivery to all critical customers.
* Defined & documented Veridicom 8D & RMA processes - responsible for, and resolved all RMA activities; failure analysis, warranty/non-warranty issues, inventory containment & valuation.
* Resolved ground ring corrosion and delamination issues, allowing full product release - hands-on failure analysis of all production & field failure units, containment & disposition while shipping customer screened units to continue OEM manufacturing.
* Defined & documented test processing, acceptable moisture levels, product handling, inspection and shipping requirements for assembly/test & outgoing customer shipments.
* Successful completion of ISO9000 audit for Santa Clara.
Senior Staff Product Engineer, Quality Assurance Manager,
National Semiconductor/Fairchild Semiconductor, Santa Clara, CA
1990 - 1999
CMOS EEPROM products - Responsible for characterization, test and qualification. Test Engineering included ATE characterization, reliability & test program generation, C programming on in-house test system and burn-in board design & stress vector generation. Managed European, Japanese & Automotive markets. Control of offshore assembly & test and supply chain management for assembly parts, services and RMA quality issues. ISO9000/QS9000 team leader for Memory Products Division and responsible for Process Change Notification distribution and resolution as well as FMEA & 8D analysis on field failures. After promotion to QA Manager, set quality targets, metrics & methodologies as well as technical writing of ISO9000 conformance specifications, datasheets, application notes, Quality Manual and customer reliability packages.
* Automotive qualification of EEPROM families ($10M P/L), involving initial, revised and die-shrink (30% typical) releases. Consistently exceeded company objectives, finishing projects on-time and within budget resulting in uninterrupted delivery to all automotive customers.
* Converted Microwire product line from ATE tester insertion to parallel environmental testing, reducing overall test processing time by 35% without degrading screening effectiveness.
* Responsible for low-voltage characterization (VDD @1.8V) allowing sale to cellphone market.
* Analyzed & resolved all RMA field failures for Ford, DELCO, Chrysler and European market segments involving hands-on failure analysis, immediate inventory containment, initial customer 8D report within 48 hours of notification, all follow-up communication and immediate/permanent corrective actions.
* Created all product qualification and Process Change Notification packages driving Automotive product acceptance of new and existing product families.
* Ford Q1 certification of Santa Clara facility, successful completion of Automotive QS9000 audits for design & manufacturing centers involving QS9000-compliant process flows and creation of Memory Products Division Quality Manual.