Quality Engineer /Manager

Philippe Thiéfain

***** * **** ***** **** Creek Az, 85331

Phone: 480-***-****

E-mail: **********@*****.***

OBJECTIVE: ENGINEERING / SEMICONDUCTOR

Seeking a position emphasizing acquired skills, and experience including: General, Operation, Technical Manageme.

PROFESSIONAL EXPERIENCE

GILLERONT, Lille FRANCE / USA

Senior engineer 2008 to present. I Provide expertise for:

- Process / Quality control / External Quality Audit / Process Qualification

- Special equipments development, PIC programing, Solidwork,

- Multiple approaches to problem-solving by evaluating fundamental issues.

- 2009: I have introduced Jump Statistic Process Control to manufacturing and published “SPC fundamentals & 6 Sigma” a technical reference document for internal use of the company.

- 2008: M&A, I did a full investigation audit / qualification program of suppliers from Italy, Spain, Germany, Taiwan. The result of this investigation lead to a very successful and smooth transaction.

STMicroelectronic PHOENIX, AZ / USA

Engineering Section Manager (2000 to 2008) Semiconductor industry. Involving close cooperation with Engineers from a wide range of groups both within the parent companies and external. I have also run cross-functional teams and e.g., led an international Diffusion team for STM involving several sites worldwide and the associated equipment vendors. e.g., Transferred BiCMOS4 Si/SiGe / BiCMOS6 CMOS with Flash, SRAM, EPROM production processes from Europe.

In Charge of Diffusion: Atmospheric Oxidation, LPCVD (Poly ,Nitride, Teos, HTO, CVD , PECVD, APCVD, HDP, RTP, Wet cleans and associated metrology. I was providing technical leadership on SPC control, 8D, FMEA, Quality Improvement, Internal /external procedures quality audits.

Awarded in 2001 and 2004 at the corporate level for Total Quality Management:

- Excellence Team award: “Clean consolidation” and “run card elimination”

- Project Team Gold Award: “PF1 cycle time and cost saving”

- Knowledge sharing Award: “Process technical committees”

WHITEOAK SEMICONDUCTOR INFINEON / MOTOROLA. RICHMOND, VA/ USA

Process Engineer (1997 to 2000). Startup of semiconductor process unit: WhiteOak, “Fab of the year 99”, high volume DRAM, SRAM manufacturing.

- Set up, qualification of new tools: SVG AVP/ TEL vertical furnaces.

- Full implementation of SPC and 6 sigma methodology for furnaces process control.

- Increased 33% production productivity by process recipe optimization and Sic high capacity boat implementation.

- Member of GOI Quality group for Continual Improvement Process, I have successfully reinforce the communication channel between production sites, Germany, Taiwan and USA, by organizing internal conferences, and international meeting.

PROMOS SEMICONDUCTOR SIEMENS / MOSEL HSINCHU, TAIWAN / CHINA

Process Engineer (1997 to 1997). Startup of PROMOS a DRAM, EEPROM production site in Taiwan (ROC), with the International Transfer Team Management, as process Ion Implantation expert. In charge of Taiwanese engineers, the technology transfer has been implemented with success and 100% of electrical parameters related to I2 were in specification.

CORBEIL SEMICONDUCTOR IBM ESSONNES / FRANCE

Production Engineer LUNA PROJECT  (1994 to 1996) Cross-functional team leader in the diffusion module, (Manufacturing, Equipment, and Engineering) to ensure an optimum production level, yield , and process qualification to PCRB.

High level of tool utilization between 85%and 95% has been achieved by using Continuous Productivity Improvement and “4 Partners analysis” method.

Manufacturing Shift Supervisor (1991 to 1994) LUNA project, a 16M DRAM startup IBM-SIEMENS-TOSHIBA join venture. In charge of 25 associates and 5 technicians in diffusion, awarded for production improvements: Test wafer reduction and Qualification frequency diminution.

Manufacturing Shift Supervisor (1989 1991) Back End Photo, in charge of 25 associates. I have reduced the “NPR’ lead time from 5 to 3 days, by implementing Quality Team management techniques.

Process Engineer (1980 to 1989) Start up of the first CMOS process unit in Corbeil-Essonnes, as process engineer in charge of Ion implantation. Providing operating and training support to manufacturing. Working within collaboration of integration and development group I have developed a charging test site to optimize electron flood gun and taught IBM internal class on “Ion implantation”.

PUBLICATIONS

- IBM Technical disclosure bulletin Vol 27 N# 4a Sep 1984 Electrostatic guttering”

- IBM Technical disclosure bulletin Vol 32 N# 12 May 1990 “Silicid Formation improvement’

- STM Technical publication 14th International Conference on Ion Implantation “Charging effects on medium current implanter on CMOS and Mixed signal IC’s  Sep 2002”

- STM Technical publication 14th International Conference on Ion Implantation “Dick temperature effect on electrical characteristics of implanted mono-crystalline emitter bipolar transistor Sep 2002”

EDUCATION / LANGUAGES

- INSTITUE UNIVERSITAIRE DE TECHNOLOGIE REIMS “Mesures Physiques”,

(Bachelor of applied physics certified in USA)

- SIEMENS class: “Management level 1” CARY, NC.

- Statistical data exploration ANOVA & regression Methods using jump SAS institute Inc.

- ISO 9000 – Internal Auditing J.Sargeant Reynolds community College

-Statistical Process Control John Tyler Community college

- DB, SQL, PHP, PIC, Solidwok certification

- Electrical drafting Certificate of professional aptitude

- USA certified Private Pilot license

- French (Fluent) English (Fluent)

Oxidation / Diffusion / Rtp / Lpcvd: Poly, TEOS, Silicone Nitride/ Implant/ Wet clean / PECVD, HDP, CVD: TEOS ,Silicon Nitride. Full knowledge of AVP-VRT / SVG / TEL / furnaces / CFM / DNS wet bench / Quantox / SILC / CV characterization /Metrology/ Management / Work method

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