ASIC Design, SOC Architecture, Low Power Design, Director
Resume:
Mohamed Allam
Coquitlam, BC, V3K 0A9, Canada
Email: *******@*****.***
Phone: +974-****-****
An experienced designer and team manager With 15 years experience in ASIC design. I am seeking a system architect position with an innovative company.
Education
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- Ph.D. in Electrical and Computer Engineering, University of Waterloo, Canada, 2000
- Thesis title: “Low-Power High-Performance Digital VLSI Design Methodologies”
- M.A.Sc. in Computer Engineering, Cairo University, Egypt, 1995
- Thesis title: “Task Allocation in Multiprocessor Systems using Hopfield Neural Network”
- B.Sc. in Electronics and Communications Engineering, Cairo University, Egypt, 1992
- Graduation Project: “Design of PLC (Programmable Logic Controller) using Intel Microcontroller (8051) and Actel FPGA chips”
- Grade: Distinction with honor. Ranked 4th out of 262 students.
R&D Experience
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- SOC and embedded systems architecture and design
- ASIC and mixed signal design, including synthesis, STA, DFT, layout and packaging
- Low power digital design
- Computer and microprocessor architectures
- Wireless communication protocols and design
- Power efficient networking and multimedia streaming
- Graphics and video processing techniques
- Hardware Virtualization and cloud computing
Work Experience
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- Principal System Architect, QUWIC, Doha, Qatar, Jul 2010 – present
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- Managing the development of baseband and protocol stack IP for LTE wireless technology.
- Defining the IP requirements and architecture. Currently working on design of the baseband hardware and an FPGA based prototype to evaluate the IP functionality
- Technical Director, Teradici Corporation, Burnaby, Canada, Mar 2005 – Jul 2010
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- Managed the chip design team and the development of various company projects.
- Architected various company products and worked with customers on developing future roadmaps and end user solutions.
- Planned and supervised the company IT resources, infrastructure and services.
Project: Chip Architect and Leader for Second Generation PCoIP device
- Defined the architecture of the chip and the interaction between the various subsystems on the chip. Defined the system architecture and interaction with the hypervisor and management applications.
- Managed the evaluation and acquisition of the various IP components and services required for the chip. That included PCIe controller, standard cells and IOs, DDR controller and phy, on chip memories USB phy/controllers and layout/ packaging services.
- Supervised the development and verification of the various blocks in the chip
- Worked with marketing on reviewing the chip and system architecture and features with various customers.
- Managed the emulation board design and the emulation efforts of the various subsystems in the chip.
- Managed the interaction between the hardware team and other development teams in the company (firmware and software).
- Device stats: 24M Gates in 65nm TSMC GP process, 3 embedded MIPS cores, 2 high end image compression/ decompression engines and x8 PCIe gen 1 interface.
Project: Chip Architect and Leader for Multi Rate SerDes Test Chip
- Architected and implemented the chip design. Defined the digital interfaces for programming and testing the analog SerDes.
- Managed the layout contractor and the interaction with TSMC
- Overseen the validation board design and bring up of the chip
- The chip achieved its objectives and proved the functionality of the SerDes blocks. This chip is being used as a part of the emulation platform for the second generation PCoIP device.
Project: Image Engine Architect and Design Lead for First Generation PCoIP Device
- Managed the R&D efforts to develop image/video compression algorithms optimized for PC user interface. The algorithms are also optimized for ASIC implementation.
- Developed a new system bus architecture to optimize the interaction between the image engine blocks and the chip memory controller.
- Managed the layout effort and the interaction with the layout contractor. Executed the static timing and vector generation for the whole chip.
- Helped develop the various CAD flows and design procedures for the company.
- Helped develop the reference design for the chip and debug customer board designs and bring up efforts.
- The chip was rev A success and was used by IBM, Dell, Cisco, HP, Samsung and many other customers.
- Leader, PMC-Sierra, Burnaby, Canada, Jan 2000 – Feb 2005
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- Led the architecture of multiple chips and subsystems.
- Initiated a company wide effort for enhancing power estimation and optimization techniques in PMC Sierra digital designs.
- Created lunch learning sessions to help educate employees about various company products.
Project: Team Lead for Fast Device Bus (FDB) Development for Shaggy SOC Device
- Worked with a team engineers on defining the specifications and functionality of high performance low latency system bus for telecom specific SOC chips.
- Managed a team of designers to implement and verify the FDB system interface and develop various SOC interface blocks based on the FDB system bus.
- Designed implemented a PCI 2.3 controller/ bridge with FDB interface.
Project: Device Architect and Lead for Athena VOIP SOC Device
- Worked on the device architecture definition and IP evaluation for the chip.
Project: Block Designer and Device Lead for SUNI-9953 Chip
- Designed the POS-PHY Level 4(TM) (PL4)/SPI-4 Phase 2 system scheduler.
- Led the development of revision B and C of the chip and moving the chip to production phase.
- Developed the ATE tests and helped debug them on the tester.
- ASIC design engineer, Nortel Networks, Ottawa, Canada, Sep 1998 – Jun 1999
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- Developed power estimation flow for DSP chips and designs.
- Worked on the optimization of special purpose DSP blocks for G.lite ADSL modems.
- Teaching Assistant, University of Waterloo, Waterloo, Canada, Jan 1996 – Dec 1999
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- Canadian Microelectronics Corporation (CMC) Teaching Assistant for VLSI CAD tools and circuit design techniques.
- Assistant Lecturer, Computer Engineering, Cairo University, Egypt, Oct 1992 – Dec 1995
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- Taught the following courses: computer architecture, logic design, software life cycle and graduation projects.
- Teaching Assistant, Computer Science, American University , Cairo, Egypt, Apr 1994 – Aug 1995
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- Taught logic design course and electronics laboratory.
Technical Skills
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Technical Skills
- ASIC design flows and tools like VCS, Design Compiler, Power Compiler, PrimeTime, TetraMax, DFT Compiler and ICC.
- Low power design, estimation techniques and tools.
- SOC architectures and mixed signal designs.
- Design and operation of standard interfaces and peripherals like: PCIe, DDR, Ethernet, USB, Flash, SPI, I2C, UART, AXI , DVI/HDMI and DisplayPort.
- FPGA and post production debugging capabilities.
- Video processing and decoding techniques
- Programming languages: C, C++, Perl and TCL.
Personal Skills
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- Strong communication and leadership abilities.
- Excellent analytical capabilities.
Publications
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- One patent awarded and several IEEE journal and conference papers. List of publications is available upon request.
Awards Received
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- Faculty of Engineering Scholarship (FOE) for five consecutive terms (Winter 1997- Summer 1998), University of Waterloo.
- International graduate scholarship, Winter – Fall 1996, University of Waterloo.
- Dean’s List Award, 1989-1992, Faculty of Engineering, Cairo University.
Volunteer Experience
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- IT support for BCMA and Tricity organizations 2001- 2010.
- Teacher at Waterloo multicultural school, 1996 – 1998.
- President and instructor at CEEE (Club of Electrical and Electronics Engineers), Cairo, Egypt, 1990 -1994.
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