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Design Engineer

Location:
Bangalore, KA, 560085, India
Salary:
industry norms
Posted:
August 14, 2012

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Resume:

K. N. SHESHARAMAN

B.E (E&C), M.Sc[Engg] (VLSI System Design)

E Mail:- hmleiy@r.postjobfree.com Phone: 998-***-****

Career Objective

To pursue a meaningful and challenging career in the field of VLSI that enables to acquire knowledge and work towards organizational as well as personal growth.

Academic Qualifications

• M.S (by Research) courses completed and awaiting results at VIT University (76.5 % aggregate so far).

• M.Sc[Engg.] in VLSI System Design, Coventry University, UK in April 2007 with 68% (Award with Merit).

• B.E in Electronics and Communication Engg. Visweswariah Technological University (VTU) in 2005 with 67.8%.

• P.U.C from Karnataka Pre-University Board at Vijaya P.U College, Bangalore in 2001 with 65%

• S.S.L.C from Karnataka Secondary Education Examination Board at Bangalore Higher Secondary School, Bangalore in 1999 with 80.16%.

VLSI tools used

Synopsys: Design Compiler, Primetime, Primepower, IC Compiler

Cadence: RTL Compiler, CTE, SOC Encounter, Nanoroute, Spectre, Virtuoso, Assura

Mentor graphics: IC Station, Design Architect

Simulation Tools: Xilinx, Modelsim, Spice, Matlab 7.5

HDL: VHDL, Verilog

Experience

• Technical Officer – VIT University, Vellore [June 2009 – July 2012]

• Trainee - TIIT Pvt. Ltd, Bangalore, Physical design certification with Cadence and University of California, Santa Cruz [January 2008 - June 2008]

• Design Engineer – Semifi Integrated Technologies Pvt. Ltd. [ April 2007 – October 2007]

Publications

1. Shesharaman.K.N and Harish M Kittur, “A OTA based CMOS Bandpass Filter for NMR Applications”, International Journal of Electronics, Taylor and Francis series, U.K.

2. Shesharaman.K.N and Harish M Kittur, “A 180 nm Low Power CMOS Comparator for Sigma Delta A/D Converters”, International Conference on Computational Intelligence and Communication (ICCIC 2012), ISBN 978**********, (Best Paper Award)

3. Bijoy Babu, Shesharaman.K.N and Harish M Kittur, “Power Optimized Digital Decimation Filter For Medical Applications “, International Conference on Advances in Computing and Communications (ICACC-2012),Cochin, Kerala, India, ISBN 978**********/12.

Patents

1. Shesharaman.K.N and Harish M Kittur, “A CMOS Continuous Time Sigma Delta ADC for MRI Receiver System”, 1118/CHE/2012, India.

Books published

1. Shesharaman. K. Narayanan, “Digital PLL for Audio Applications – Based on ASIC Low Power & FPGA Flow”, LAP LAMBERT Academic Publishing, Germany, ISBN-10: 384-***-****.

Projects

1. Sigma delta modulator for MRI receiver system

Tools : Spectre, Virtuoso, Assura

Technology : TSMC 180 nm, 7 metal layers

Role : Design, Schematic entry, DRC & LVS

Description : The design involves the analog design flow to meet the target specifications. The design is targeted to 180nm TSMC technology with low power methodology and good resolution involved.

2. Multi feedback Band pass filter

Tools : Cadence- Spectre, Virtuoso, Assura

Technology : TSMC 180 nm, 7 metal layers

Role : Design, Schematic entry, DRC & LVS

Description : The work involves the design, layout of OTA and Multi feedback band pass filter for its use in the Magnetic Resonance Imaging receiver system with low power as the key consideration.

3. USB Wrapper

Tools : SOC Encounter XL, CTE, Nanoroute

Technology : TSMC 90 nm, 5 metal layers

Design Size : 520K gates, 5 macros, 3 clocks

Role : Floor-planning, P&R, CTS, Timing Closure

Description : The design process was targeted to meet slack & skew by various timing optimization techniques. The design was analyzed for placement and routing congestion & other relevant issues connected with the design. After some floor-planning and placement iterations the results were found to meet the requirement.

Personal Details

Date of Birth : 05-Oct-1983

Father’s Name : Narayanan K

Marital status : Single

Languages Known : English, Hindi, Kannada, Tamil



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