Engineer System

FAYEZ M. SHANTANU

***** **** ****, ******, ** ***17, Cell: 858-***-****, email:*********@*******.***

OBJECTIVE:

Advancement of my career and industrial experience in the field of IC System Validation/Design and Product Engineering.

PROFESSIONAL SUMMARY:

• Diligent, detail and result oriented engineering professional

• More than 6 years of system design verification, post-silicon validation and product engineering experience

• Worked closely with Architecture, Design and verification engineers to set up bench validation infrastructure and led silicon debug and characterization.

• Developed flow and infrastructure to validate low-power technologies on the DSP processors and as well implemented and ported several power benchmark applications to run on silicon and gather power and performance metrics.

• Worked closely with Software Engineers to resolve software and firmware related issues for silicon products.

• Assembly coding experience in ARM (ARM940T and ARM9TDMI), x86 processor and in-house DSP processor.

• Knowledgeable with ATE and board-level system validation and characterization process.

• Successfully completed post-silicon validation, characterization and documentation processes to release products to production ramp.

• Knowledge of embedded systems and DSP architectures.

• Advanced knowledge and understanding of using silicon debug tools and as well performing system-level debug through external interfaces such as JTAG and ETM.

• Experience in system-level debug on architecture-based simulator, RTL simulation and FPGA-based emulators.

• Knowledge of engineering statistics and analysis.

• Worked with DFT engineers to develop and enable debugging capabilities such as scandump and memory cache dump features for post-silicon debug purposes.

• Proven experience as a team member or individual contributor in silicon debug, validation, and characterization.

• Knowledge of engineering statistics and analysis

• Hands-on experience on several lab equipments such as oscilloscope, signal generator, spectrum-analyzer, Bit Error Rate Tester, frequency counter, Logic analyzer, video measurement scopes, etc.

• Performed testing and debugging on customer returns.

EDUCATION:

University of Kansas Lawrence, Kansas

Master of Science in Computer Engineering (GPA: 3.81/4.00) July 2004

Bachelor of Science in Computer Engineering (GPA: 3.34/4.00) May 2002

WORK EXPERIENCE:

Senior Engineer November 2007 - Present

Qualcomm Inc, Austin, Texas

• Participated in the silicon bring-up for Qualcomm DSP processor for several modem chipsets.

• Developed test code in assembly language for the DSP and ARM processors to validate various core units.

• Developed automation scripts in perl to run regression tests on silicon and auto-generate test status reports.

• Developed low-level JTAG instructions to enable several debug features on DSP processor.

• Setup a debug infrastructure for various products through the JTAG interface to enable the DFD features such as scandump, cache memory dump, cycle stretch and event clock stop for software and firmware debug purposes.

• Extensive usage of the Lauterbach debugger tool for system-level validation and characterization purposes.

• Implemented “shmoo” generation tool and test coverage report for random generated fmax test cases using the Lauterbach debugger tool for system-level characterization and correlated with the data captured on ATE.

• Wrote up test plans to run various tests to perform functional validation for various core units with directed test cases and setup test metrics to verify silicon corner cases.

• Developed several directed test cases to validate DSP processor core units such as cache thrashing, TLB setup, DDR memory interface, AHB, AXI master/slave ports and other sub-system units.

• Implemented an automation infrastructure from scratch to automatically build and compile the industry DSP benchmark applications such as dhrystone, FIR and other multimedia applications with the latest gcc compiler toolset released by the software teams and run them using the DSP processor on various silicon products.

• Wrote performance tests to measure memory and bus latency on the DSP processor.

• Worked with Architecture, Design and Verification teams to design test cases for functional validation and as well engaged with various teams during silicon debug process.

• Worked on DSP power analysis such as verification of system clock gating functionality for low power mode.

• Implemented methodology and test code to validate AVS (Adaptive Voltage Scaling) functionality on DSP processor and correlated the power data with respect to DCVS (Dynamic Clock switching and voltage scaling) software routine.

• Wrote power test cases such as Max power and voltage droop tests to analyze current transient behavior and used such test case to compare power variations against DSP benchmark applications such as FIR, FFT and dhrystone.

• Participated in several debug sessions with internal and external customers and developed a methodology and procedure to test, debug and analyze the customer returns.

Platform Validation Engineer June 2007 – November 2007

Intel Corporation, Folsom, California

• System level debugging in Linux environment for Chipset products.

• Supporting the automation infrastructure and perform regression test on different platform configurations.

• Familiar with BIOS configuration to set up different parameters for chipset configurations.

• Execute and debug concurrency, CPU matrix and Power Management tests on chipset platforms.

• Knowledge on PC and chipset (north/south bridge) system architecture.

Product/IC Validation Engineer April 2005 – June 2007

Conexant Systems Inc., San Diego, California

• Embedded ARM firmware programming in assembly and C/C++ using SDT/AXD Debugger.

• Source control and bug tracking using Starteam.

• Troubleshooting complex system issues for System EVK/DVT systems and on SoC systems.

• Timing analysis and protocol validation of high speed interfaces such as SATA and PCI-E and DDR SDRAM.

• Bench validation of I/O functions and power consumption of the chip across process, voltage and temperature. This includes functional operation and timing validation of peripherals such as I/O Bus, SDRAM memory, Transport Stream interfaces, JTAG, GPIO, I2C, USB, encryption engines (AES, DES) and clock outputs.

• Validate and characterize the SATA PHY for TX jitter, RX jitter tolerance, Eye mask measurements, ATEST voltage/current bias measurements and power state switch test.

• ATE data characterization on mixed signal IC products using Agilent 93k and Teradyne Catalyst Tester. ATE data was collected for all production tests across voltage, temperature & process; analyzed the data using Datapower.

• Automated Bench test setup using LabView to characterize ICs across process, voltage and temperature.

• ATE data characterization and analysis using DataPower for ATE Final Test, QA, and Probe Limit generation.

• Yield and PCM data analysis using DataPower and process re-target for yield improvement.

• Support Test Engineers to improve final test coverage for outgoing devices.

● Assisted in cost reduction of products with FAB transfer (TSMC to SMIC) where processes included PCM data analysis, ATE & bench characterization across process, voltage and temperature.

Hardware Research Engineer (Summer Internship) May 2003 – August 2003

BioComp Systems Inc., Lawrence, Kansas

• Configured a PanelLink Receiver SiI161B board to interface with a LED projection driver

• Configured a GENerator LOCKing (GENLOCK) graphics adapter to synchronize the True-3D image

Graduate Teaching Assistant August 2002 – May 2004

Electrical Engineering and Computer Science Dept., University of Kansas, Lawrence, Kansas

Planned, demonstrated, and taught microprocessor labs for undergraduate students

Experiments included assembly programming for Motorola HC12 processor

SKILLS:

Programming Languages: C, C++, Perl, shell scripting, LabView, Jscript, Assembly, JTAG

Silicon Debug tools: Lauterbach Trace32 debugger, JTAG, ETM, scandump, memory dump.

Operating Systems: Linux, Unix, Windows

Statistical Tools: DataPOWER

Laboratory Equipments: Tektronix Oscilloscopes, Current probes, Tektronix VM700 video analyzer, Tektronix TG2000 pattern generator, Anritsu BERT, Agilent Signal Generator, LeCroy SDA, Multi-ICE tools, ITP, Logic Analyzer and Spectrum Analyzer

MASTERS RESEARCH:

Development of hardware and software for a low-cost True-3D volumetric display system

• Built a color multiplexing hardware using the HC12 processor and high-speed analog GaAs switches

• Interfaced color multiplexing hardware system with the GENLOCK graphics adapter for True-3D color display

• Implemented software using MATLAB and OpenGL to display sequential 2D frames of the True-3D image

PROJECTS:

Snapdragon QSD 8650 (65 nm):

- next generation DSP processor bring-up and functional validation of the DSP core units.

- Developed and ran several directed and random generated fmax test vectors and characterized these test cases across PVT (process, voltage and temperature).

- Implemented automation infrastructure to run several DSP benchmark software applications and generated test reports.

- Participated in several show stopper customer return issues and was able to debug and analyze cause of failure and worked with design teams to provide workarounds.

Serial ATA test chip (90 nm):

- Bench validated and characterized the SATA Physical layer across process, voltage and temperature for Transmit Jitter, Receiver Jitter tolerance, Eye mask measurements and Power State Switch tests.

Broadcast MPEG-2 Audio/Video Decoder (0.15 um):

- Supported Toshiba & LG Electronics in ironing out their audio/video system issues.

- Helped Test Engineers to improve test coverage on ATE test program to catch the various test escapes seen from the RMAs returned from customer.

- Completed bench & ATE data characterization and generated limits for the ATE test program

Front-end Cable Modem STB (0.15 um):

- Bench validated peripherals such as PLL, DES, AES, PHS, CableCARD, Transport Stream Engine, I2C bus, ARM (940T & 9TDMI) and SDRAM controller across process, voltage and temperature.

Contact this candidate