Project Pvt Ltd

Ranjith Bidri

________________________________________

Cellular 997-***-**** #3992/14, Anjenaya Layout,

************@*****.*** near MES Convent,Davanagere,

Karnataka 577001

Career Objective To gain as much knowledge in the field of engineering as possible so that I am able to improve on my creativity as well as all the other innovative skills and meanwhile also benefit the company with whatever I have learnt in the past and whatever I will learn during my presence in the company.

Current Status Project Trainee at Whizchip Design Technologies Pvt Ltd, Bangalore(1 Year Experience)

Education MS in VLSI CAD

Manipal Centre for Information Science, Manipal

With an aggregate of 8.17 CGPA

B.E, Electronics & Communication 2009

Bapuji Institute of Engineering & Technology, Davanagere, Karnataka. With 62.46%

P.U.C, PCMB 2005

STJ P U College, Davanagere, Karnataka, with 66.00%

S.S.L.C 2003

Bapuji High School, Davanagere, Karnataka. With 72.48%

Successfully completed coursework in self-directed, self-paced learning environment.

Implant Training

Completed training in VLSI front end design and verification VEDA IIT, Hyderabad as part of internship at Whizchip Design Technologies Pvt Ltd, training covered Advance Digital Design, Verilog, System Verilog, Synthesis, Perl & Basics of UVM.

Subjects of interest

Logic design, Digital design using Verilog, System Verilog for verification.

Computer Exposure

Platforms: Windows, UNIX

Hardware Description languages : Verilog, System Verilog

Tools: Questasim, VCS, NC-Verilog, Design Compiler

Personal Skills

• Can work effectively in a group as well as individual and take up

responsibilities.

• Good listener, willingness to learn.

• Team facilitator and hard worker.

Project Details

Current Project

• Title : To Build Monitor for Transactions between MAC and PHY Layer in USB3.0

• Language: System Verilog

• Duration : Nine months

• Details: Data, Status and Command signals from the PHY Layer are sent to the monitor block where signal checking, CRC checking and validation of various packets is done. Driver block gets these signals from monitor block through mailboxes. User is provided with a access to inject error to various packets in driver block and these error injected packets are then sent to MAC layer of USB3.0

• Mentor : Pranip Kumar H T (Senior VLSI Engineer), Whizchip Design Technologies Pvt Ltd, Bangalore

MS mini projects

Semester 2

• Title: Design of DMA controller using Verilog HDL.

• Language: Verilog

• Duration: Three months

• Details: The DMA controller can issue commands to the memory that behave exactly like the commands issued by the CPU & it is dedicated to an I/O function. The DMA controller connects one or more I/O ports directly to memory. Four DMA channels are considered and arbitrated with priorities.

• Guide: Chaitanya V S (Faculty, MCIS, Manipal)

Semester 1

• Title : Implementation of FIR filter

• Duration : Three months

• Details: The main objective of the project is to learn this powerful technology and to present VLSI architecture for implementing finite impulse response (FIR) digital filters. The scope of this project includes the simulation of low pass FIR filters using spice and magic tools which are the powerful VLSI design tool. The design mainly includes, designing of

Delay units

Multiplier section

Adder section

• Guid: MadhuShankar M (Faculty, MCIS, Manipal)

Engineering final year project

• Title: Location Based Wild Animal Intrusion Alarm System

• Duration: Three Months

• Role: Managed and directed a team of four, successfully completing the project on-time and under budget. Earned a reputation as a valuable and cooperative coworker by: being fair, honest, and willing to help others when needed; effectively resolving conflicts at appropriate times; and assisting to become familiar with policy and operations.

• Sponsored by KSCST (Karnataka State Council for Science and Technology),IISc Bengaluru and also selected for state level KSCST Project Exhibition 2009 held at NIT Suratkal.

Personal Details

Name : Ranjith Bidri

Father name : Rajashekar Bidri

Mother name : Pramella B R

Date of birth : 19 Aug.1987

Age : 24 years

Nationality : Indian

Languages known : English, Hindi, Kannada.

Declaration

I hereby declare that the above mentioned details are true and correct to the best of my knowledge.

(Ranjith Bidri)

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