Design Pvt Ltd

CURRICULAM VITAE

G. HARISH KUMAR

Address: D: no: 12-4-318, Santa pet, Nellore.

Telephone: (Res.) 080********.

Email: ******.***@*****.***

Date of Birth: Nov 17th, 1988

Snapshot: currently doing internship as DFX Validation trainee in INTEL TECHNOLOGIES PVT

LTD, Bangalore during MTECH final semester project work.

Pursuing MTECH in VLSI DESIGN from VIT University, Vellore.

Objective: To Associate myself with an esteemed organization and to accept the challenges in the job by utilizing my education, analytical skills more meaningfully and work hard towards achieving the goals of the organization.

Educational Qualifications:

Degree/ Examination Institute/Univ./Board Year of Passing Percentage Remarks

M.tech

(VLSI Design) VIT UNIVERSITY

Vellore 2012 8.72(CGPA) --

B.Tech

(E.I.E) Narayana Engg College

(JNTU, Anantapur) 2010 75.8 Dept Rank

03

Intermediate

(M.P.C) Nalanda Junior College

Nellore 2006 78 --

SSC Everest Eng Med High

School, Nellore 2004 60.85 --

INTERNSHIP DETAILS:

Company : INTEL TECHNOLOGIES PVT LTD

Period : SEP 2011 - JULY 2012

Subject : DFX Validation Trainee

Credits : MTECH II year Project work.

MTECH Thesis:

1. “DFX METHODOLOGY FOR SoC ARCHITECTURE” carried out under the guidance of Prof. Mr. Harish Kittur M department of SENSE, VIT University and Mr. K.M.G. Madanmohan, DFX lead, INTEL Technologies Bangalore during SEP –MAY 2012.

Tools: SPYGLASS DFT, SYNOPSYS: DFT COMPILER, DESIGN VISION

MENTOR GRAPHICS: FASTSCAN

Description: The principal objective of this approach is as follows: 1) To improve the quality of design by simulating based on DFT logic integrated verification at the RTL level. 2) Improve robustness of Silicon quality by detecting the escaped bugs in pre-silicon phase are identified during post-silicon validation. 3) To reduce the die space and its complexity of instrumented test logic with efficient techniques.

Research Experience:

MTECH Dissertation:

1. Paper on “HARDWARE ANALYSIS OF FASTEST FIR FILTERS” Work carried out under the guidance of Prof. Arun Kumar, Department of VLSI, VIT University during JULY- NOV 2010.

.

Tools: ISE (XILINX) using VERILOG and Matlab

2. “DESIGN AND ANALYSIS OF 4KB ARRAY CELL FOR THE DEVELOPMENT OF SRAM CHIP” Work carried out under the guidance of Dr. Harish.M.Kittur, Department of VLSI, VIT University during Jan- April 2011.

Tools: Design Architect (MENTOR GRAPHICS) with ELDONET Simulator.

3. Lab Project: “Four Bit ALU” Work carried out using VERILOG in LAB sessions under MTECH curriculum.

Tools: RC and Encounter (CADENCE) using VERILOG

Description: To Design the architecture and code for given Specification and perform

Frontend and backend analysis and finally obtained the layout for design.

BTECH Thesis:

1.“Evolution and Modeling of User performance for Pointing and Scrolling on Hand Held Devices using Sensors” carried out under the guidance of ASST Prof. Prasanthi Priyadarsini.M, Department of EIE, NEC during Jan-May 2010.

Tools: Visual Basics and Embedded C

Industry oriented Mini Project:

“Design and Development of Distributed Control Systems” carried out under the guidance of T. Kamal Kumar, PED Department at BHEL, HYD, ANDHRA PRADESH during Apr-May 2009.

Technical Skills

Languages : C, VERILOG, Basics in Assembly Lang programming, PERL scripting.

Tools : Xilinx ISE, Design Architect and IC Station, RC and Encounter.

Software : Xilinx, MODELSIM, Mentor Graphics, TINA-TI, Spy Glass and Cadence.

Work experience: RTL level DRC clean, DFT concepts, SCAN DFT insertion using SYNOPSYS

DC, Coverage reporting using DVE, ATPG using Mentor Graphics,

Other skills : Good Documentation & Presentation skills and debugging Ability

Area of Interest:

Digital IC Design,

ASIC Design,

Low power IC Design,

Memory Design.

Strengths:

Strong determination, Desire, Punctuality, Interpersonal Learning and Team skills.

Hobbies:

Gardening, Dance, watching cartoon movies, listening music, cooking.

Academic activities:

Published a Paper on “Hardware analysis of fastest FIR filter Based on MRAM” in the “International Journal of Micro and Nano Systems” Conducted by Karunya University, Coimbatore, on 18th Mar’2011.

Participated in national level Paper presentation on “Bio Sensors” organized by RGM Institute of Technology, Nandyala, Andhra Pradesh, on 13th Mar 2009.

Extra Curricular Activities:

I got 1st prize in International SET conference under Department of VLSI Conducted by VIT University on 20th -21st Apr 2011.

Got Intel Corporation Instant Recognition Award from Madan Mohan Kadabagala Mallappa Gowda for understanding the ATPG flow, closing the opens/ Issues in SCAN insertion and ATPG testing to meet the coverage > 96%.

Personal Details:

• Father Name : Mr. G.Sathyanarayana.

• Date of Birth : NOV 11-1988.

• E-mail id : ******.***@*****.***

• Nationality : Indian

• Languages : Telugu and English

Known

References:

Dr. Harish.M.Kittur Mr. Kadabagala Mallappa Gowda, Madanmohan

Professor DFX lead,

School of Electronics Engineering, WWID: 11272973,

VIT University INTEL TECHNOLOGIES PVT LTD, Bangalore.

Tamil Nadu, India. Bangalore.

E-Mail: ******@***.**.** **********.**********.********.*****@*****.***

Declaration:

I hereby declare that the above furnished information is true to the best of my knowledge.

Place: Vellore (G. Harish Kumar)

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