Software architect/developer/engineer

V N Pradeep Kumar Kaja

**** * ******** **,***#**04,Chicago,IL-60612. 1-312-***-**** *******.****@*******.***

Summary

• Designed, analyzed and tested VLSI circuits using cadence (schematic, virtuoso, spectre and diva) tools and Atalanta.

• Strong knowledge in characteristics of MOSFET and CMOSFET based digital circuits.

• Excellent communication, leadership and interpersonal skills, a team player with good analytical skills.

Education

Master of Science University of Illinois at Chicago (Jan 08 – May 10)

Major: Computer Engineering Current GPA: 3.76/4.0

Bachelor of Engineering Sathyabama University (Aug 03 – May 07)

Major: Electronics & Communication Engineering GPA: 3.85/4.0 (86.67%).

Skills

Programming Languages : VHDL, Verilog, Perl Scripting, MATLab, C, C++ and Java.

Design Automation Tools : Cadence (Schematic, Virtuoso, Spectre and diva), Altera Quartus II, VPR with T-VPack, Xilinx

ISE 11, ALDEC Active HDL 7.2.

Others : H-SPICE, Synopsys Scirocco Simulator and DC , ATPG-Atalanta, P-SPICE, Cygwin, PCSPIM.

Projects

Test Compression and Compaction

• The Fully Specified and Compacted test vectors for ISCAS 89 sequential circuits are obtained from ATPG and ordered

using MATLAB for minimum switching between vectors.

• The Ordered test vectors are then encoded using EFDR technique in MATLAB which gave a compression of 10% and

they are written to ATE.

• The De-compressor for RLE encoding technique is coded in VHDL and tested using Active HDL and synthesized using

XILINX ISE Webpack.

ATPG & Fault Simulation Functionalities

• Generated Test Vectors for ISCAS85 benchmark circuits using Atalanta.

• Simulated the circuits with same number of random generated vectors and compared with fault coverage of ATPG

generated test vectors.

• Increased the number of randomly generated test vectors and understood the variations in fault coverage.

• Compared the run times for ATPG generated and randomly generated test vectors.

4-Bit Universal Shift Register

• Schematic of a 4-Bit Universal shift register is designed using schematic in Cadence tools.

• Layout was designed using virtuoso cadence tools and the LVS was matched with each other.

• It was recognized as the best project in terms of the area and delay, where we calculated area as 4492203 sqlambda

and delay as tphl = 0.27ns and tplh = 0.13ns.

• Designed without involving any adder circuitry during shifting the bits.

Retiming Synchronous Circuit

• Written a java application to retime a synchronous circuit which is in blif format and gives the output also in blif.

• The output blif file is given to T-VPack which packs the FF’s and LUT’s into Logic blocks.

• The .net netlist file obtained from T-VPack is given to VPR which gives the placed and routed output files.

• The given synchronous circuit is retimed by reassigning the registers using VPR & T-VPack and decreased its time

period from 21esec to 13esec.

• Achieved a 9esec retimed circuit for the given circuit with no constraint on number of registers that can be added.

Simulation Project Using Simple Scalar

• Executed 32*32 Matrix multiplications on individual processors.

• Calculated the performance of individual processors using inbound and outbound execution.

Synthesized 16-Bit Comparator

• A 16-Bit comparator is structurally and behaviorally coded in VHDL and simulated with Synopsys Scirocco simulator

using inputs read from an input file and given to the comparator.

• The codes are Synthesized using Xilinx ISE Webpack 11 and have done TIC (total gate input cost) comparison.

• The total real time taken for Xilinx synthesizer is compared for structural and behavioral implementation.

32-bit Booth Multiplier and Add & Shift Multiplier Simulation

• The Multiplier is coded in VHDL using both Booth’s and Add & Shift algorithms and compiled using Active HDL.

• The Test benches which generate random 25 inputs for both the algorithms individually are coded and simulated.

• The test bench also reports for errors and then the % time improvement for booth’s implementation is calculated.

Designed a Two Input Finite State Machine

• A Moore state diagram is drawn for two input finite state machine which gives output only when it notices a four 1’s

and three 0’s on corresponding inputs.

• The obtained FSM is coded using VHDL with different process for next state, output, current state and clock process.

• A test bench is coded in VHDL for random application of input vectors and the output is time analyzed.

Designed a CPU, CMI and Memory Unit

• Behaviorally described the 16 Mb RAM which consists of 32 bit registers addressed in VHDL and it is initialized with

specified values on an external signal.

• The CPU-Memory Interface (CMI) takes care of fully responsive communication between the memory and CPU.

• The CPU fetches data from memory unit on an external signal and processes it and stores back in memory.

Automatic Railway Signaling

• Developed a new sensor, a combination of thermistor and spring, to sense the rail weight and friction heat

• This reduced the cost of existing IR sensor by 5 times.

Papers & Course Work

Literary Survey on DFY

• Learnt how to analyze yield using the Poisson’s and compound poisson distributions for chip consisting of two

different types modules with redundancy and chip kill circuitry, this can also be applied to more number of

modules.

• Understood how the introduction of redundancy in memory and logic circuits affects the yield.

• Studied the techniques such as layout and floor-plan modification for improvement of yield in logical circuits.

Other Papers

• Written a paper as required for the course work on efficient conversion of Solar to electrical energy using SWNT.

• Gained knowledge on H-SPICE by doing different experiments on OP-Amp’s.

Work Experience

• As a Graduate Assistant maintained database and website for MSCS Department of UIC. (Aug 08 - May 10)

• As a Program Analyst Trainee for Cognizant Technology Solutions (CTS) learnt SQL, Informatica. (Aug 07 - Nov 07)

Relevant Courses

Testing & Reliability for Digital Systems Physical Design Automation

Advanced VLSI Analog VLSI

Introduction to VLSI Digital System Design

Advanced Computer Architecture Computer System Design

Nano Electronics CAD Based Logic Design

Computer Organization II

Achievements

• Won the Inter College Chess Title twice.

• Played as hockey goal keeper in Inter College championship.

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