Project System

RESUME

Paridhee Aggarwal

Mob: +91-962*******

Email: ********.****@*****.***,

********@******.***

Objective:

To pursue a successful career in the field of VLSI Design and Verification, by continuously learning new technologies and using them to enable the organization achieve it’s goals.

Career Summary:

• 8 Months work experience as an ASIC Design and Verification Engineer Trainee at CVC Pvt. Ltd. Bangalore, (September 2011 till date)

Professional Experience:

Projects:

Project 1: Verification of AMBA 3.0 Advanced Peripheral Bus [APB] using System Verilog and VMM

This project involved the RTL development of the APB 3.0 Master and Slave modules, and their verification by designing a constrained Random verification test-bench using System Verilog, System Verilog Assertions and VMM. Code coverage and functional coverage were also measured.

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Project 2: Verification of I2C using System Verilog and VMM

This project involved the verification of the I2C IP, by designing a constrained Random verification test-bench using System Verilog, System Verilog Assertions,VMM and Advanced VMM (VMM RAL, Multi Stream Scenarios(MSS)). Code Coverage and functional coverage were also measured.

Project 3: Verification of SPI using System Verilog and OVM

This project involved the verification of the SPI IP, by designing a constrained Random verification test-bench using System Verilog and OVM.

Project 4: Verification of VME using System Verilog Assertions

This project involved the verification of the VME by developing System Verilog Assertions.

Project 5: Verification of PWM using System Verilog and OVM

This project involved the verification of the PWM IP, by designing a constrained Random verification test-bench using System Verilog and VMM.

Academic Projects:

• 6 months Project in "Ultrasonic Snow Depth Sensors” from DRDO (SASE), Chandigarh.

This sensor is used to measure the snow depth. This is a microcontroller (89C51 or ADUC847) based project in which I used Ultrasonic sound waves to transmit and receive the data.

• Minor project on “Railway Crossing System with GPRS Technology”.

Technical Skills:

• HDVL Languages Known : System Verilog , SVA, VMM, OVM ,Verilog, VHDL

• Programming Languages known: C ,C++

• Simulation Tools known: VCS/VCS-MX, DVE, Questasim, Modelsim, NCSim, Riviera

• Synthesis Tools Known: Xilinx ISE 9.1i.

Academic Qualifications:

• B-Tech in Electronics and Communication from B.G.I.E.T Sangarur, affiliated to Punjab Technical University, Jalandhar (2006-2010) with 74.68%.

• Intermediate (XII) in 2005 with 1st Division (60.02%) from UA Board, Nainital.

• High School (X) in 2003 with 1st Division (69.66%) from UA Board, Nainital.

Seminars/ Workshops attended:

• Seminar on “Science and its Development” conducted by BGIET on 23rd and 24th December 2006 in Sangrur.

• Workshop on “National Level Technical Festival” conducted by BGIET on 16th January, 2007 in Sangrur.

• 6 weeks training in CNC System from BHEL Haridwar, Uttarakhand.

(Introductory knowledge of CNC Systems)

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