Engineer Design

Mehdi Si Moussa

****, ****** *********, ***. ***

Montréal (Québec) H3S 1W5

514-***-****

********@****.***

French, English, Arabic, and Spanish

SUMMURY

Design of RF integrated circuits in CMOS technology (Distributed amplifiers, LNAs, VCOs...) including simulations, layouts drawing, and measurements.

Electromagnetic simulations of passive components

RF characterization of passive and active devices on SOI CMOS technology

Drawing of RF layout circuits on 130 nm CMOS SOI process.

Verification of Mask Design using Calibre LVS and DRC programs.

High temperature characterization of RF circuits and devices

5 years experience in R&D, state-of-the-art CMOS technology, for RFIC

Ability to work in a deadline-oriented environment

Ability to work well independently and in a team

Very good communication and organization skills

WORK EXPERIENCE

2010 - RFID Designer ÉTS, Montreal

RFID system analysis and evaluation

- Optimization of RFID system deployment

Feasibility studies/prototypes/projects

- Study of tags integration for biomedical applications

- Designed state of the art RFID tags using HF WORKS 3D Solver

2008 - 2008 RF Designer ADVANTECH AMT, Montreal

Design and development of power amplifiers for satellite communication systems

- Project Engineer of a C, X, Ku Band power amplifiers

- Verification of BOM, coordination with production

2006-2007 Post-Doctoral Fellow at EMIC laboratory

UNIVERSITÉ CATHOLIQUE DE LOUVAIN, Belgium

Design of low power-low consumption RF circuits for standards

like ZigBee (2.45 GHz) in CMOS SOI technology

- A 2-mW Power Consumption Low Noise Amplifier in PD SOI CMOS Technology

Optimisation of passive devices in CMOS SOI technology

- Temperature Behavior of Spiral Inductors

- Silicon-on-Insulator (SOI) transistors (130 nm PD, FB, BC and DTMOS) behavior for high temperature applications

2002-2006 Research Assistant at EMIC laboratory

UNIVERSITÉ CATHOLIQUE DE LOUVAIN, Belgium

Design and modeling of RF and microwave circuits in CMOS SOI

technology

Improve circuits performances in term of gain and bandwidth by

reducing losses of passives (Transmission lines, Inductors).

- Behavior of TFMS and CPW line on SOI substrate versus high temperature for RF applications

- Behavior Spiral Inductors on High Resistivity Substrate in SOI CMOS Technology

Design of fully integrated distributed amplifiers on 130 nm CMOS

SOI technology (DC to 30, 40 and 50 GHz) in collaboration with

ST Microelectronics France.

- A 7 dB 43 GHz CPW Distributed Amplifier on 130 nm CMOS SOI (IEEE MTT Mar. 2008).

- A 7 dB 27 GHz TFMS Distributed Amplifier on 130 nm CMOS SOI (IEEE MTT June. 2006).

- A 10 GHz Distributed Oscillator in 130 nm CMOS SOI (EuMC 2006).

Introducing ESD protection in Distributed amplifiers and LNAs on

CMOS SOI process, in collaboration with Sarnoff Beligum.

- Design of a Distributed Amplifier with On-chip ESD Protection Circuit in 130 nm SOI CMOS Technology

- A 2.4 GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 130 nm CMOS SOI CMOS (IEEE MTT Dec. 2007).

Writing scientific and technical papers in international conferences

and journals (IEEE Member)

EDUCATION

2006 PhD, Microwave & Microelectronics

UNIVERSITÉ CATHOLIQUE DE LOUVAIN, Belgium

Thesis "CMOS SOI DA for New Communication Systems"

http://www.emic.ucl.ac.be/People/PersoPage/PHD_Mehdi_SiMoussa.pdf

2001 Master's Degree, Microwave

ÉCOLE NATIONALE POLYTECHNIQUE, Algeria

1999 Engineer, Electronics

ÉCOLE NATIONALE POLYTECHNIQUE, Algeria

SOFTWARE SKILLS

ADS, ICCAP, Cadence, IE3D, ELDO, Microwave Office, HF Works

Windows, Unix, Latex, Matlab

HOBBIES

Traveling, movies, Reading, music

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