Software QA Analyst/Engineer

(Mangal) - Madhumangal Javanthieswaran

**-1-503-***-**** *.***********@*****.*** http://www.linkedin.com/in/madhumangal

SUMMARY:

• Hardware Engineer with 2 years experience in FPGA design and verification seeking a position in Design automation, HW/SW product development or component design and validation.

• Expertise in Constrained Random Verification (CRV) for VMM.

• Proficient in High level Synthesis, Logic Synthesis, Schematic capture, Code coverage, RTL coding, Formal Verification, Software & Hardware design validation techniques and overall ASIC & FPGA design flows.

TECHNICAL KNOWLEDGE:

Programming and scripting Languages : C, C++, Perl, PHP

ESL, Hardware Description and Verification Languages : Verilog, SystemVerilog, VHDL, SystemC

Design, Simulation and Verification tools -

High Level Synthesis : CatapultC, SynphonyHLS

Logic Synthesis : Xilinx-ISE, Altera-Quartus II

Schematic capture : OrCAD, TannerEDA, PADSsuite, ExpressPCB

Functional Verification : ModelSim, Synopsys VCS

Formal Verification : 0-In Formal Verification

Transistor Level Simulation : PSPICE

Other Tools : SIMULINK & MATLAB, NI- LabVIEW, AutoCAD

Business courses : Total quality management, Principles of management, New venture management

PROFESSIONAL EXPERIENCE:

Part Time:

Web Developer, Center for South Asian Studies – University of California, CA July 2010 – Present

Tools: Linux, PHP, Smarty templates, Apache web server, MySQL, HTML, CSS, Adobe-Dreamweaver

• Responsible for site architecture/ backend development using open source toolset (i.e. LAMP) and front end development with CSS and HTML/XHTML.

• Introduced the use of project management software to coordinate the workflow between the client and off-site designer

• Performed basic network troubleshooting using Windows (ipconfig) for the purpose of testing, installation of wireless Netgear Routers and Print Servers (Linksys WRT54G, Netgear FVS318 and PS101) including VPN Configurations, static/DHCP IP Configurations and MAC Address Filtering.

• In addition to code development, assisted in creation of project documentation and overall maintenance of http://southasia.berkeley.edu/ website.

Technical support staff – I – University of Portland, OR Aug 2008 – May 2010

Tools: MS Office, Linux, UNIX, Windows, Mac OS X, Cisco-webex

• Responsible for Microsoft Windows desktop support and network connectivity for 250 users. Troubleshot, analyzed, resolved tickets and closed 95% of in-bound requests within 20 minutes.

• Evaluated new information systems, products, and services to improve end-user experience.

• Configured and upgraded networks and network peripherals, routers, switches, printers, fax machines, monitors, and various audio-visual (A/V) devices.

• Implemented efficient procedures for problem identification, tracking, documentation, assignment, and close-out that reduced ticket resolution time by 75%.

Full time:

FPGA Hardware Design Engineer - Gemini Communications Ltd, Chennai, India Jun 2006 –May 2008

Tools: Verilog, Xilinx ISE, ModelSim

• Participated in hardware design review and developed test plan. Developed self check verification

• PCI Express Hard IP Verification for Stratix IVGX FPGA. In charge of DPRIO functional tests that configure PCIe HIP. Developed directed test benches using Verilog

• Development of Test Bench for BUS Interface Model for MC68030 and MC68020

• This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made.

EDUCATION:

• Master of Engineering, Electrical Engineering May 2010

University of Portland, Portland, OR GPA 3.56/4

- Member of IEEE, University of Portland Branch

• Bachelor of Engineering, Electronics and Communication Engineering May 2007

Anna University, Chennai, India (Top 10% of class) GPA 3.6/4

- Elected the Chairman of IEEE STUDENTS BRANCH, Anna University, Chennai

- Awarded the Exemplary Recognition Award by IEEE STUDENTS BRANCH for my Voluntary services

- Won First Prize in the Senior Design Project competition conducted by IEEE STUDENTS BRANCH

- Won Second Prize in ELEXPO project competition conducted by IEEE STUDENTS BRANCH

ACADEMIC PROJECTS:

Design of a Satisfiability solver to check for satisfiability of a Boolean equation

Tools: Turbo C, CollabNet-VCS (Version Control System), Microsoft Office – Visio & Word

• The satisfiability solver program, checks for satisfiability of a given Boolean equation upon reading a CNF (Constrained Netlist file).

• The developed C Program reads the variables in a Boolean equation and checks the satisfiability for all possible 2n input combination in a given ‘n’ variable Boolean equation. The program then returns variable assignments which satisfy the equation.

Design and implementation of FPGA based keyboard – LCD interface

Tools: Verilog & VHDL, Xilinx - ISE, CollabNet-VCS (Version Control System), Microsoft Office – Visio& Word

PCI Express Hard IP Verification

• Participated in hardware design review and developed test plan. Developed self check verification

• PCI Express Hard IP Verification for Stratix IVGX FPGA. In charge of DPRIO functional tests that configure PCIe HIP. Developed directed test benches using Verilog

• Performed onsite installation and maintenance of various RFID readers and equipment.

• As a Project Lead - Designed, Synthesized and Simulated two multi-million gates, Standard Cell ASICs (A 0.11 Micron, 4 Million Gates, and a 0.18 Micron, 1.9 Million Gates) for SAN/Fibre Channel applications (1/2/4 Gbps). Designed over 700K Gate's of Digital Logic. Played a leadership role in managing these projects -- by dealing with ASIC vendor, verification group and design engineers. Performed DRCs, RTL Analysis, Synthesis, Netlist generation and other front end ASIC functions.

• Evaluated ACTEL, XILINX and CROSSPOINT FPGA software. Developed and Presented two days training (hands-on) course to engineers on use of ACTEL's FPGA technology. Taught Mentor's V8 Tools and VHDL classes to engineers.

High Speed Serial Interface to Quad and from Quad to HSSI

• Involved in automation of complete ASIC design flow from Netlist to GDSII.

• Worked on command files setup, data analysis, error fixing at various stages of P & R flow viz. placement, optimization, clock tree analysis, routing and timing analysis.

• Assisted in execution, analysis and debugging of Stratix II GX 130, 60& 30 device POF tests and connectivity checks - both from High Speed Serial Interface to Quad and from Quad to HSSI for all the families of Stratix II GX.

• Created top –level test bench to instantiate the DDR3 Soft IP, Verilog Schematic netlist and UDIMM/PCB Delay Models to validate Statix III interfaces at system-level. Designed and developed basic DIMM model, scan shift register block and random delay generation modules in Verilog.

• Collaborated in the creation, enhancement and maintenance of scripts used in backend flows. This includes Perl scripts for pre/post – processing timing results, hold fix insertion location search, collecting overall test results in 50 modes.

Parity generation on a PowerPC 603 address bus

• Modified behavioral VHDL logic of an existing PowerPC 603 CPU simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications.

• Designed VHDL logic code that enhanced the 603 CPU model by generating an internal address bus busy signal when an address-only phase is initiated by the ASIC.

• Developed 200+ C test cases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including CPU and PCI address space, SRAM, cache, BAR and other registers.

• Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic.

• Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency & voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers.

References are available upon request

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