Project Design

Sheetal Sood

Flat *, Royal Castle

*th Main, *th Cross, Kodihalli

Bangalore –560008

Phone : 080-********(Residence)/994-***-****( M)

Email: *******@*****.**.**

EXPERIENCE Around 4 Years in Layout,4 years in Physical design.It include design and verification for different technologies 0.18, 0.13, 0.12, 0.09,0.065 and 0.045,0.032,0.022um & foundries like TSMC, ACT1, TI,INTEL.

Library development: Standard cells, I.O’s, Gate Arrays

• Physical layout verification-Calibre:DRC,LVS

Hercules : DRC,LVS,ANTENNAE etc.

• Place & Route: ENCOUNTER,ICC

• Physical design :STA,Timing and DRC closure of design.

• Synthesis and P&R till gds.

SKILLS

(Tools / Languages / Methodologies)

Place & Route : Encounter, ICC

Layout design: Tanner – LEDIT,

Cadence-Virtuoso,Encounter

Extraction: STAR-RC

Layout Verification: caliber,Hercules.

Schematic Entry : Cadence

Synthesis :DC-TOPO

Simulation: CHAMOTO (Inhouse tool for characterization in INFINEON)

Languages:

HTML, DHTML,

Operating System: Windows, UNIX

Assembly Language : Microprocessor –8085

OBJECTIVE To gain more knowledge in the field of ASIC Layout Design and to pursue a career in implementing the same with a goal to actualize the product. Looking for part time layout design position.

EDUCATIONAL QUALIFICATIONS

• Electrical Engineering: BTech from REC (Regional Engineering College –Hamirpur - Himachal Pradesh-Presently functioning as NIT) with 72% marks.

EMPLOYMENT HISTORY:

3 months worked In I2IT at Pune

Done 1 yr VLSI COURSE.

Nov 2002 to May 2004: Spike InfoTech Pvt. Ltd. Bangalore.

JUNE 2003 to April 2004: worked in Texas Instruments in onsite projects from SPIKE.

April 2004 till September 2005: Infineon technologies.

September 2005 till December 2011: Intel technologies.

WORK EXPERIENCE :

INTEL: Worked in intel technologies for Layout cleanup, Synthesis, Place and route, Extraction, Verification :worked from synthesis till gds .Worked from TNET0 to FSO and further in Eco’s(Base as well as Metal steppings).Timing and routing closure of design using synopsys tools DC topo,ICC,PT-SI, cadence Encounter and other inhouse tools.

INFINEON TECHNOLOGIES INDIA : Worked in std cell layout using virtuoso. Worked for characterization.

Attended one month training in MUNICH (GERMANY) for standard cell group – including Layout design, P & R and CHAMOTO (Characterization tool) training.

SPIKE INFOTECH:Done layouts for standard cells for various technologies.

Projects done in INTEL:

SANDYBRIDGE(p1268/32nm)/IVYBRIDGE(p1270/22nm)/HASWELL(p1270.2/22nm):Sandybridge,Ivbridge and Haswell are integrated graphics sitting with processor. Sandybridge is 32nm and other two are 22nm process differing only in metal stalks 8 to 10.In sandybridge I was responsible for layout cleanup of three partitions. In Ivybridge and haswell I am responsible for timing/routing/caliber closure (max_cap,max_tran and other advance process node checks) for 2 partitions.Partition sizes were approximately 1.2 to 1.4 million gates having multiple clock domains.Fastest clock was running at 2.6GHz.

CRESTLINE(90nm)/CANTIGA(65nm)/IRONLAKE(45nm) These are integrated graphics sitting in north bridge along with Memory controller .All chips have DDR interface and PCI/PCIE interface.My responsibility was mostly to do APR (Encounter /ICC compiler ),Extraction (STAR-RC)and Layout cleanup using ICC compiler.

Projects done in Infineon:

Full Custom Layout & Generation of Backend views using Magma.

Attended one month training in MUNICH (GERMANY) for standard cell group – including Layout design, P & R and CHAMOTO (Characterization tool) training.

1.) Design of layouts for STARFLEX library in 90 nm and same in 65nm.Handled full libraries for layouts and also responsible for backend views generation using MAGMA blastfusion. These libraries are subset of normal starlib library. These contain flexible filler cells and is useful while ECO implementation.

2.) Layouts for retention flops: Double height layouts for standard cell group with best optimized in area and for power optimization.

3.) Analogstarlib library: (65 nm ): Done layouts for 65nm for this library as well as participation in architecture decisions and issues .

4.) I/O ‘s : Done layouts for I/O team for c11FL PROJECT : Done layouts for high performance CMOS Process for digital applications with embedded flash memories.

TEXAS INSTRUMENTS INDIA: CMOS Core Cell Library Development:

1. GS50 TI Standard Cells Library for 0.12um Technology : 175 cells

2. GS50H_DELTAL TI Standard Cells Library for 0.13um Technology :680 cells

3. GS50H_DELTAL_PM (Power Management) TI Double height retention flops and latches for 0.13 Technology :68 cells

Responsibilities: Development of layouts for Simple to Complex cells with

aspects like, Porosity, Cell area minimization, alignment of

polys,increase source contacts,minimizing routing congestion

yield enhancements etc.

DRC, LVS and Electromigration checks.

Skill : Cadence Layout Editor, Schematic Composer,

PROJECTS DONE: IN SPIKE INFOTECH:

1.Virage Logic NXT Standard cell for TSMC 0.13Technology, Nov - Dec 2002

This project involved creating layouts for 480 cells for 0.13u Technology

Responsibilities: Development of layouts for Simple to Complex cells with aspects like pin accessibility, Cell area minimization, minimizing routing congestion,yield enhancements etc. Responsible for creating the layouts and physical verification DRC and LVS.Team members: 6

2.Virage Logic NXT Metal-Programmable Cells for TSMC 90nm Technology, Jan 2003

This project involved creating layouts for 400 cells for 90nm technology Responsibilities: Development of layouts for Simple to Complex cells with aspects like pin accessibility, Cell area minimization, minimizing routing congestion,yield enhancements etc. Responsible for creating the layouts and physical verification DRC and LVS.Team members: 6

3.Virage Logic Standard Cells Library for TSMC 90nm Technology, Mar 2003

This project involved creating layouts for 320 cells for TSMC 90nm technology

Responsibilities: Development of layouts for Simple to Complex cells with aspects like pin accessibility, Cell area minimization, minimizing routing congestion,yield enhancements etc. Responsible for creating the layouts and physical verification DRC and LVS.

4.ACT1 0.18um technology From NEXFLASH, Feb - Mar 2003

This project involved designing of block level layouts.

Responsibilities: Designed hierarchial level blocks with minimum block area from the leaf cell level layouts. We have designed low voltage, high voltage transistors with different Mask Layers and different sizes of resistors. To avoid latchup, Guard Rings are placed around the transistors. Physical verification by using Dracula- DRC / LVS.

5.Virage Logic Standard Cells Library forTSMC 0.18nm Technology, April 2003

This project involved creating layouts for 385 cells for TSMC 180nm technology

Responsibilities: Development of layouts for Simple to Complex cells with aspects like pin accessibility, Cell area minimization, minimizing routing congestion,yield enhancements etc. Responsible for creating the layouts and physical verification using Calibre DRC and LVS.Team Members: 6

6.IWATT 0.35 Polycide Process (For Low Power Circuits) May -2003

This project involved creating layouts for 50 cells for 0.35u technology

Responsibilities: Development of layouts for Simple to Complex cells with aspects like pin accessibility, Cell area minimization, minimizing routing congestion,yield enhancements etc. Responsible for creating the layouts and physical verification DRC and LVS.Team Members: 4

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