****, * ******** ****., *** 110, Tucson, AZ 85719
Phone: (520) ***-****
EDUCATION Master of Science (M.S.) - Electrical and Computer Engineering, University of Arizona.
Graduation Date: May 2011, CGPA: 3.75/4
Bachelor of Engineering (B.E.) - Electronics and Communication Engineering, Anna University.
Graduation Date: May 2009, CGPA: 81%
Graduate: Introduction to Algorithms, Operating Systems, Computer Architecture, Distributed Computing,
Computer Aided Logic Design, Random Process for Engineering Applications, Engineering of Computer
Based Systems, Digital Image Analysis.
Undergraduate: Data Structures in C, Object Oriented Programming, Microprocessors and Microcontrollers,
Computer Organization, Computer Hardware and Interface, Embedded Systems
Languages: Proficient: C, C++, MATLAB
Beginner: Java, Perl, Verilog
Architecture: x86, MIPS, DLXOS
API: CUDA, SystemC, OpenMP, MPI
Tools: GNU, SVN
Graduate Teaching Assistant Aug 2010-Dec 2010
Department of Electrical and Computer Engineering, University of Arizona
Teaching Assistant for course ECE372-Microcontroller Design. Responsibilities include assisting students in
developing small projects using PIC24 microcontroller which was programmed in Embedded C using MPLab.
MAILBOX AND MULTI-LEVEL FEEDBACK QUEUES FOR DLXOS
Implemented message passing interface using mailbox for processes to communicate in a distributed memory
system. Also implemented a multi-level feedback queue for process scheduling. The multi-level feedback queue was
implemented to prevent resource starvation by a single process. (DLXOS, C)
MONITOR LIKE SYNCHRONIZATION FOR DLXOS
Implemented a monitor-like synchronization using locks and conditional variables to address the bounded buffer
problem. Using locks, mutual exclusion is guaranteed and using conditional variables, dependencies between various
processes are sorted. (DLXOS, C)
EDGE DETECTION FOR PARALLEL FRAMEWORK
Implemented Sobel Edge Detection Algorithm using shared memory (OpenMP) and distributed memory (MPI) model
obtained up to 5x speedup. Then implemented the same algorithm in CUDA kernel and obtained up to 90x speedup
(CUDA, OpenMP, MPI, C)
HIGH LEVEL SYNTHESIS TOOL
Designed and implemented a high-level synthesis tool capable of creating a synthesizable high-level state machine
(HLSM) description in Verilog from a C-like sequential program supporting conditional and loop constructs while
providing various scheduling alternatives. An Efficient file parsing function was written in C to read a generic C like
sequential file (C, Verilog, Xilinx ISE)
SYSTEM-LEVEL DESIGN OF HARWARE/SOFTWARE PARTITIONED APPLICATION
Implemented the matrix multiplication application as a hardware/software partitioned design consisting of software
component, hardware co-processor and memory communicating over a shared bus using SystemC and Transactionlevel
modeling (SystemC/C++, TLM)
SYSTEM-LEVEL DESIGN OF FIR FILTER
Implemented a system-level design of FIR filter using SystemC and Transaction-level modeling and did time accurate
performance estimation (SystemC/C++, TLM)
ADVANCED HIGH-PERFORMANCE BUS
Implemented Advanced Microcontroller Bus Architecture - Advanced High-Performance Bus (AMBA-AHB) in
Archulator framework to study the change in the performance of the Archulator. The basic archulator framework
consists of processor core, system bus, instruction and data cache all implemented using SystemC (SystemC/C++,
AUTOMATIC LICENSE PLATE CHARACTER RECOGNITION
Developed software which recognizes the character present on the license plate and displays the license information
to the user. A template matching algorithm was used to match the characters extracted from the license plate to the
original characters. Totally 36 templates were used to account for both alphabets and numbers (MATLAB)
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