Raju K Contact Address

+91-80-267***** ( Res ) #28, 2nd cross,

+91-0-973-***-**** (mobile) Eshwar Nagar

E-mail: ek99z3@r.postjobfree.com Banashankari 2nd stage

DOB: 25th august 1979 Bangalore-70

SUMMARY:

8+ years experience in software development

Skill Sets:

Skills:

- C/C++, STL, Boost, Makefiles, Tcl/TK, Qt, Parsers, Data structures an algorithms.

- Experience in design automation for DFT

- Good fundamental understanding on ASIC flow, design methodologies in DFT, backend methodologies in placement/routing, DRC.

- Oasis import/export for Magma Talus.

- RTL-GDS2 flow using Magma Talus.

- Experience in Matlab & Simulink.

Platforms and Debuggers:

- Linux, Solaris, Visual studio, gdb, ddd.

Configuration management systems:

- cvs,clearcase

Work Experience:

The MathWorks, Inc Bangalore

January 2011 to Present

Designation: Senior Software Engineer

o My work responsibility is mainly in Simulink Core Engine, feature development for Model based design basically worked on core block development for simulation, Lead role in configuration management tool development.

o Development is mainly in C++, Matlab , SDLC process is followed for each projects.

Magma design Automation India Pvt ltd Bangalore

May 2008- December 2010

Designation: Member of Technical Staff

o Tool for optimizing Memory footprint for talus-vortex

Designed and implemented memory profiler for profiling used-memory at command level / full run. I have integrated google-tcmalloc API’s, libunwind package etc to get the memory profiler done. The tool was capable of providing both textual and graphical output. There was another effort for bringing down memory foot print, which was done by changes in some low level data structures. There was a savings of 8 bytes because of this.

o Maintained hierarchy robustness for flattened database

The main aim of this project was to correct all the errors/corruption which may arise during the flattening of design. If there are any inconsistencies it is supposed to report the error message to application, designed the tool such that it reports errors for all corner scenarios.

o Padring inter-row routing/ staggered bonds support in Magma

Staggered bond cell placement wasn’t supported earlier; I designed and implemented this feature. For inter row padring routing objective was to connect adjacent pins of identical pad cells which are facing each other separated by inter row spacing.

o Special cell placement for decaps

I have worked on enhancements related to placement of double height decaps without violating DRC’s and OD filler placement for 28nm designs(special cells inserted on top and bottom of macros for 28nm designs). Both of these changes involved significant low level changes.

o OASIS import /export in Magma

The main aim in this project was to add support for importing/exporting of new industry standard mask layout format- OASIS. Added embedded compression for OASIS with CBLOCKS with zlib internal API’s, it resulted in 3X compression of oasis files

.

LSI Logic India Pvt ltd Bangalore

June’05 – April 2008

Designation: Senior EDA Software Engineer

o Support for Virage flow in Memory BIST:

Worked on enhancements like supporting of bist only flow with virage integrator, synthesis script generation, automatic parsing memory configuration files, automatic synthesis of memory collars in parallel etc. Supported design centers in all the issues related to memory BIST.

o Support for logic vision based flow in MemoryBIST

Worked on projects like qualification of design compiler version 2006-6-sp1 for synthesis of memory collars, support of power management mode operation with self time enable and disable functions, test bench modification for simulation, automatic script generation for simulation with various memory compilers. Also gained fundamental understanding in memory compilers.

o Flex Stream Liberty Infrastructure

Obseleting proprietary library representation and supporting of Synopsys liberty was main aim of the project, But it was very involved project starting from requirement gathering to testing. It also involved some low level sensitive changes to database related API’s and core functions. Also it required some changes in GUI code (TK), DFT application code (TCL).

o verilog reader/writer runtime improvement:

Verilog reader was taking huge runtime if we have designs with more than 10k Ports; I have re written some parts in the algorithm to improve the runtime. A runtime improvement of ~10X observed for designs with large number of ports.

C2silicon India Pvt ltd Bangalore

Member of Technical Staff (April ’04 – June’05), Client: IPFlex Japan

As a contract employee from Insight CAD (Sep’03- March’04)

o Placement and routing tool development:

This tool was used for placement and routing for a reconfigurable processor

Called DAP/DNA, It was written in C++ and Python. It involved coding for placement algorithm and interfacing simulator through SWIG.

o Descreen porting from C to DFC:

The original descreen modules is written in C language, it is used to eliminate half tones from the scanned images in the Xerox machine. The aim of this project is to redesign and optimize C code and port into DFC (C based synthesis) environment

Insight CAD pvt ltd Bangalore

Software Engineer

May ’03 to March ’04 .

o SystemVerilog 3.1 parser:

This was implemented in C++, Flex, and Bison. It is a basic parser which can parse full Systemverilog BNF, Store it in our own database..

o Interfaced Verilog with SystemC using PLI interface, done simulation of some of the IP’s which has both verilog and SystemC models.

ISRO Bangalore

Project Trainee –Academic project

Sep 2002 to April 2003

o Partitioning Techniques in VLSI circuits:

Aim of this project was to develop a VLSI circuit-partitioning algorithms with reasonable run time, which can divide a given circuit into user specified number of blocks with minimum interconnection between them I have done a good research on various partitioning algorithms, and chosen 3 partitioning algorithms (FM, Multiway FM, NGSP) for implementation, benchmarked the runtime with some real huge designs.

Academic Performance:

MS – VLSI CAD, Sep 2001-Mar 2003

Cumulative 80.2%

Manipal Academy of Higher Education (A Deemed University), Manipal, India

B.E - Electronics & Communication, Mangalore University (KVG college of Engineering)

(Year of Passing Aug 2000) Cumulative 68%

Reference:

Available on request

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