Mudasar Resum

RESUME

Objective:

To give the best out of my skills, utilize my Potentials to the fullest and strive for my professional Recognition which would contribute and enhance the growth of the organization.

Key Strengths:

Strong Interest and enthusiasm in development and design of Organization.

Ability to take complete accountability and responsibility for any task assigned to me and completes it on time with hard work and sincerity.

Continuous learner from every available source, books,

Articles, internet and people.

Academic Profile:

M.Tech [VLSI]

Jawaharlal Nehru Technology (71.26%)

Anantapur.

2009-2011.

B.Tech [E.C.E]

Jawaharlal Nehru Technology

Graduated with First Class (65.26%).

2004-2008.

Higher Secondary Education

Completed with First Class (80.8%).

2002-2004.

High School Education (SSC)

Completed with First Class (79.8%).

2002.

Soft Skills:

Hardworking With Positive Attitude.

Adjust to the new Environment and Situations.

Eager to know new technologies and new things.

M-Tech Project:

Project Title:

CMOS FULL ADDERS FOR ENERGY EFFICIENT ARITHMETIC APPLICATIONS.

Energy efficiency is one of the most required features for modern electronic systems designed for high-performance and/or portable applications

The power-delay product (PDP) metric relates the amount of energy spent during the realization of a determined task, and stands as the more fair performance metric when comparing optimizations of a module designed and tested using different technologies, operating frequencies, and scenarios.

Applications:

Digital signal processors (DSP) architectures and Microprocessor.

Cellular phones, PDA’s, and laptop computers require the use of power efficient VLSI

Circuits.

Technical Skills:

Diploma in an ASIC/FPGA Design for duration of 6 months in Vector Institute, Hyderabad.

Languages: C, C++.

Operating Systems: Windows XP, Linux.

Hardware Languages: Verilog, ASIC Flow ,System Verilog,vhdl, FPGA.

Tools for ASIC:

Simulation: Modelsim, Questa.

Synthesis: Design Compiler.

STA: Primetime.

ATPG/EDT: Testkompress.

Tools for FPGA :

Simulation: Modelsim, Questa.

Synthesis: Precision RTL, Leonardo Spectrum, synplify.

Place & Route: Xilinx ISE, Altera Quartus.

Other Tools :

MBIST Architect, LBIST, BSD.

Physical verification/DRC/LVS : Calibure Suite.

Achievements:

Participated in a “NATIONAL LEVEL CONFERENCE” Organized by

“KALASALINGAM UNIVERSITY”, Tamil Nadu.

Participated in a “NATIONAL LEVEL CONFERENCE” Organized by Lords College Of Engineering and Technology, Hyderabad.

Hobbies:

Watching and Playing Cricket, Reading Technical related books and Articles.

Declaration:

I here by declare that all the information mentioned above is true to the best of my Knowledge.

Date: 30-06-2011

Place: Hyderabad

(Mudasar Basha)

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