Design Training

GauravYadav

Mobile: 097********

Email id:*************@*****.***

Address: D-70, Sec-D, L.D.A colony,

Kanpur road, Lucknow (U.P.)

Career Objective:

Intend to build a career in organisation with committed & dedicated people, which will help me to explore myself fully and realize my potential and to apply my management, technical and interpersonal skills and further refine them.

Summary:

1. VLSI training (4 months) from Maven silicon.

2. Knowledge of System Verilog,Verilog,FPGA tools.

3. M.B.A. from Lucknow University (2011).

4. Done B.E. in Electronics Communication (2008 pass out).

5. Completed as a Trainee in R.D.S.O. Lucknow from July2007to August 2007.

6. Delivered seminar on Digital Circuits,Network Security&Mobile Communication.

7. Ability to Work in a Group as well as independently with a minimal supervision.

8. Good interpersonal and organizational skills.

Summary of Qualification:

1. Good understanding of the ASIC and FPGA design flow.

2. Experience in writing RTL models in Verilog HDL and Testbench in SystemVerilog.

3. Very good knowledge in verification methodologies.

4. Experience in using industry standard EDA tools for the front-end design and verification.

VLSI Domain Skills:

HDLs : Verilog and VHDL

HVL : SystemVerilog

TB Methodology : UVM

EDA Tool : Modelsim and ISE

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis

TRAINING:

IN B.E. :

Organisation R.D.S.O ,Lucknow

Period July 2007 – August 2007

Background

Study of communication modes used in railway department.

Study of various equipment: Optical Fiber Communication, Train Traffic Control Equipments, Microprocessor Lab, Digital Exchange, Advance Equipment for Radio & Wireless Communication for period July- August 2007.

Major Project

Completed major project on “Car Countering Vehicle Kidnapping through Cellular Mobile”.

Education Profile:

Qualification University Year of Passing Percentage

M.B.A Lucknow University 2011 66%

B.Tech(EC) Rajiv Gandhi ProudyogikiVishwavidhyalaya, Bhopal. 2008 66%

Basic Computer Course ET&T Lucknow 2002

12th Std U.P. Board 2001 56%

10th Std U.P. Board 1999 58%

Additional Qualifications:

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore ,Year: FEB 2012

Experience

NOV 2011 – FEB 2012, Maven Silicon, VLSI Design and Training Center

VLSI Projects

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Real Time Clock using Verilog HDL independently

• Architected the class based verification environment using SystemVerilog

• Verified the RTL model using SystemVerilog.

• Generated functional and code coverage for the RTL verification sign-off

• Synthesized the design

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Dual Port Ram using Verilog HDL independently

• Architected the class based verification environment using system Verilog

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

UART- IP Core – Verification

HVL : System Verilog

EDA Tools: Modelsim.

The UART IP core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various control and status registers. This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode. It is an interface between wishbone compatible UART transceiver, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. The UART core RTL is technology independent and fully synthesizable.

• Architected the class based verification environment using system Verilog

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

Job Details:

• Worked in “BALMER LAWRIE & CO. LTD.”.

• Worked as a company representative in marketing.

• Total work experience is seven months.

• Nature of job is to deal with clients directly, tell them about our services and also to know what our clients wants new services to us.

Achievements:

• Participated in cultural activity in college and school.

• Organised various cultural events like ”KSHITIJ” in college, which is annual program of I.T.S (Lucknow university).

Seminar:

• Presented paper on Digital Circuits in B.Tech (I sem)

• Presented paper on Network Security in B.Tech (II Year)

• Presented paper on Mobile Communication in B.Tech (IV Year)

Personal Information:

Date of Birth 16th June, 1984

Hobbies Travelling, Playing Cricket, Listening Music, Solving Puzzles

Languages

Marital status

Religion English, Hindi

Single

Hindu

Date:- Yours faithfully,

Place: BANGALORE (GauravYadav)

Contact this candidate