Resume

Sign in

vlsi design engg.

Location:
Gaya, BR, India
Salary:
3 to 5 lakh
Posted:
August 09, 2012

Contact this candidate

Resume:

SUNNY

M/S Radhey Ram Saryoo Prasad,

Purani Godown Gaya,

Bihar. Pin - 623001

Mobile : +91-902*******

Email ID: edzb8q@r.postjobfree.com edzb8q@r.postjobfree.com

OBJECTIVE

Looking for a position that will build-on my skills so that I can use it for the development of my organization and help me for an upward movement.

AREAS OF INTEREST:

Digital System Designs

ASIC Design

EDUCATION:

M.Tech. VLSI Design

(Pursuing)

VIT University, Vellore, TamilNadu.

7.33/10

(1st Sem.)

7.89/10

(2nd sem)

B. Tech. E&TC

Maharastra Institute Of Technology Aurangabad, Mh.

78.63 %

XII th

State Board Bihar.

73.77 %

X th

C.B.S.E.

82.60 %

SKILLS:

Programming

: Verilog HDL

Software

: ALTERA Quartus II 9.1, MODELSIM (Quartus II 9.1) Cadence Virtuoso Schematic Editor, RC compiler, Cadence Encounter.

Operating system

: Linux, Windows.

PROJECTS:

Design of Low Power BIST for Scan Based Circuit.

The aim of the project is to build the BIST circuit for the SCAN based circuits. The main principle for the design is based on the LFSR design. The produced test pattern is having a single bit change output which will ultimately reduces the testing power of the design. For the stuck at fault coverage reports of the design we used the Atalanta tool.

Tools Used: Cadence – RTL compiler, Atalanta.

Design of Single Latch High Speed Double Edge Triggered Flip Flop.

In this project low power dual edge triggered static CMOS flip flop has been designed in which data can be latched on either edge of the clock signal and by using this flip flop we can decrease the clock frequency of the clock signal while maintaining the same data rate due to which the power consumption of the circuit can be reduced in comparison to the circuit with single edge triggered.

Tool used: Cadence – Virtuoso Schematic Editor.

Design of 64 Bit Low Power and Area Efficient Carry Select Adder.

A simple modification is done in this project at the transistor level in the architecture of the carry select adder. In this project the ripple carry adder has been replaced by the BEC circuit and due to this there is a large reduction in the power and area in the adder circuit.

Tool used: Cadence - RTL compiler.

Project Trainee at PARI Robotics, (Pune).

Precision Automation And Robotics India Limited is a leading engineering and integration company in India, offering wide range of service in the field of automation mainly for the automobile company of India as well as aboard. Pursue my B.Tech final year project at PARI on “Automatic Gauging Machine” for Maruti Suzuki.

ACHIEVEMENTS:

GATE 2010 Qualified with 87.33 percentile.

Won first prize in inter-college debate competition in B.Tech.

OTHER INFORMATION:

Languages Known: Marathi, English and Hindi.

REFERENCE:

Will be furnished on request.

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge and belief.

Place: Vellore. SUNNY



Contact this candidate