Software Engineer

TUSHAR PHADKE

****, ******* ******, ***** **: 213-***-****

APT#10 Los Angeles, CA 90007 duja03@r.postjobfree.com

PURPOSE To secure a position in electrical engineering to utilize my engineering knowledge and contribute towards organization’s growth.

EDUCATION

Master of Science in Electrical Engineering GPA:3.20 May 2010

University of Southern California, Los Angeles, CA

Bachelor of Engineering in Electronics and Telecommunication May 2007

Mumbai University, Mumbai, India

RELEVANT COURSEWORK

Computer Systems Organization, MOS VLSI Circuit Design, Analog and Non-Linear Integrated Circuit Design, Computer Systems Architecture, VLSI System Design(A and B), Solid State Processing and Fabrication of Integrated Circuits, Modern solid state devices

TECHNICAL SKILLS

Programming Languages: C, C++, Verilog, SystemC ,MATLAB, Assembly (8051/85/86) ,UNIX

Applications: CADENCE Schematic, Virtuoso, ePD, HSPICE,SPICE MWAVES, Nanosim, NC-Sim, modelsim,

Scripts:TCL,PERL

Know-how

Analog circuit design and modeling, integrated circuit design and simulation, gate level simulation with timing, circuit optimization for low-power and high-speed digital VLSI, knowledge of verilog and RTL design, transistor-level analog IC design using CMOS technologies as well as Cadence, System On Chip(SOC),layout tools, DRC/LVS check, signal integrity issues, transmission line analysis

WORK EXPERIENCE

PXL Soft, Mumbai, India January ‘08- April'08

As a Software Tester and Web Tester, Tested a software (DGFOTOGALLERIA) used for image editing and tested the Webpage of the company.

Siemens Limited, Mumbai

As an Intern, worked on Railway compartment monitoring security system(Data Acquisition) as part of the under-graduate studies .Used C++, Assembly Language programming (microprocessor) . Designed and developed and tested implementation of the project

ACADEMIC PROJECTS

DDR2 memory controller design Fall’09

Designed and implemented 512MB DDR2 memory controller (500MHz) in Verilog to support features like scalar, block and atomic read/write working on Denali DDR2 model (250MHz) and simulated using NC-Verilog.

16 bit motion estimator for DSP Spring’09

Designed a 16-Bit Motion Estimation kernel for a DSP consisting of 4Kb (2×128×16) data memory, data pointer, and the absolute difference accumulator, which consists of a 16-bit absolute difference circuit and a 16-bit adder circuit, using cadence Schematic and made layout Using Cadence Virtuoso tool and simulated and tested it using Nanosim tool

SRAM Spring’09

Designed 2.408KB SRAM along with write circuit, precharge circuit and sense amplifier with 16 bit wide words using cadence Schematic and made layout Using Cadence Virtuoso tool and simulated and tested it using Nanosim tool.

Accumulator Spring’09

Designed 24 bit Accumulator using 23-bit adder and 24 bit registers and a D flip flop using Cadence Schematic and made layout using Cadence Virtuoso tool and simulated it using Nanosim tool

5 – Stage pipeline Fall’08

Designed and simulated 5-stage pipeline which supported a small set of instructions (R-type, Load/store, Branch and Jump) as a part of computer architecture course. Removed data dependencies using Hazard Detection Unit and Forwarding Unit Implemented both early branch and late branch versions of pipeline

SimpleScalar Simulation and Benchmarks Fall’08

Simulated SPEC2000 benchmarks(100million instructions) mcf (integer benchmark) and equate (floating point benchmark)

On simplescalar simulator to study characteristics of cache configuration and their effects on performance.

Analysed 3 different cache configurations to study impact of parameters like associativity, cache size on parameters like

miss rate, CPI based on simulations

Chip fabrication Fall’09

Fabricated a 3 inch wafer having chips consisting of various components like MOSFET, Resistor, Capacitor, PN diode in class 100 clean room. Tested the wafer and calculated various characteristics of devices like threshold voltage, capacitance, transconductance etc

Contact this candidate