JAMES R. STEWART
Cell: 508-***-****
Home: 508-***-****
***.****@*****.***
http://www.linkedin.com/in/jimstewart2
SUMMARY
Accomplished Systems Engineer with extensive experience in process development, medical devices, systems integration, storage systems, firmware SQA and networks. Leader able to simultaneously manage multiple projects with diverse customers and limited resources. Cross functional team player with a broad knowledge, and proven ability to solve complex issues. Recognized as an effective communicator who consistently delivers results under tight time constraints.
KNOWLEDGE
Programming Languages: Python, PERL, C and C++
Operating Systems: UNIX, Linux, Windows, VMware
Software: MS Visual Studio, Softbench, HP-VEE, Rational, MS Project and MatLab
Databases: Informix, MS SQL Server, Corel Paradox, MS Access, MYSQL
Skills: Statistical Process Control, OOD, Data Structures, Computer Architectures, LEAN, 6 sigma, Project Management, FDA GMP, QSR, ISO 13485, IEC 60601-1 & 60601-2
Certifications: Informix DBSA and Level 1 HP-UX administrator
Protocols: PCIe, QPI, IPMI, FCoE, SAS/SATA, Ethernet, 802.3, 802.11, FCP, iSCSI
WORK EXPERIENCE
EMC, Hopkinton, MA 2000 - 2011
Senior Hardware Development Engineer 2003 - 2011
IA Platforms, Global HW Engineering
Developed and led the system level DVT and firmware QA validation process (FI/FMEA) on 14 platforms and 32 products. Participated in field failure escalation teams on hardware related issues. Evaluated new technologies on prototype hardware chipsets as part of the design evaluation process. Designed and configured, 3 lab networks to support new hardware development.
* Introduced to EMC Global hardware the concept of negative type fault insertion verification testing.
* Developed the FI/FMEA process to validate EMC's Hardware, High Availability, Firmware and Software CRU/FRU diagnose-ability. FI/FMEA enables EMC's common hardware replacement strategy saving millions in replacement inventory.
* Led FI-FMEA on all of EMC's SAN, NAS, CAS and Unified platforms with as many as 19 engineers and 3 platforms at a time. Eliminated thousands of issues resulting in an uptime approaching six nines under tight resource and time constraints.
* Closed testing gaps by developing processes using protocol jammers and in-circuit emulators to functional test NMI/SMI error traps faults prior to product release.
* Designed and configured 3 lab networks which can generate any kind of traffic on LAN and WAN networks with UNIX, VMware, Windows and Linux clients supporting EMC's Global Hardware. The labs can simulate any kind of traffic pattern for any enterprise data center. Resulting in other groups such as field service and midrange systems integration copying the labs for the configuration flexibility.
* Collaborated with field service, manufacturing, software developers and hardware architects to debug numerous field failure escalation issues. Reproduced customer environments, recreated the issues, identified root cause and verified the patches resolving issues quickly with minimal downtime.
* Developed processes to qualify partner technologies such as Intel's NTB port and Asset's HSIO tool eliminating multiple issues prior to final silicon reducing partners' costs and EMC's time to market. Identified two chip errata on Intel's latest chipset.
* Prototyped EMC functionality such as the CMI path over Intel's NTB-NTB ports on reference platforms reducing issues prior to development.
* Received 4 silver awards and 5 gold awards primarily for providing hardware, firmware and analyzer support to other groups enabling resolution of issues quickly with minimal impact.
Hardware DVT Engineer, Network Storage Group 2000 - 2003
Lab manager and team lead of 5 DVT engineers accountable for creating new processes, procedures and documentation; verifying the entire Celerra system hardware functionality from hardware and firmware, up through the software to the user interface. Designed and maintained a lab consisting of UNIX, Linux and Windows servers, 2 performance stress stations and an environmental chamber. The lab could stress 16+ Celerra stations with Clariion or Symmetrix backends with ATM, FDDI, 10 / 100 / 1000BT Ethernet, iSCSI and Fibre Channel traffic.
* Reduced the time to market of new network interfaces by 3 months.
* Developed performance stress process to enhance 8 corner testing. Identified 2 additional chip errata eliminating threat of data loss. Detected and eliminated 3 errors in the kernel NMI error handler avoiding data unavailable situations.
* Received the VIP award for the lab's flexibility and ease of reconfiguration to meet new products.
AGILENT TECHNOLOGIES, Andover, MA 1993 - 2000
Formerly Hewlett Packard
Process Development Engineer, Health Solutions Group
Developed test systems and processes to characterize medical ultrasound transducers for NPI. Supervised a team of 7 manufacturing technicians who performed acoustic and impedance measurements. Utilized statistical processing techniques to reduce manufacturing scrap.
* Reduced development time by designing a Schlieren interferometer making the acoustic beam visible. A CCD camera captured the image and Matlab mapped the acoustic intensity profile. Identified a tooling alignment issue with a curved linear array. Reduced acoustic intensity mapping by 60%.
* Led design of a solid state acoustic waveform, impedance and elemental crosstalk test system reducing handling damage and manufacturing test time. The system was compliant with the FDA cGMP. Sensor manufacturing replaced 6 XYZ robots with 2 of the new systems.
* Defined and documented elemental cross talk measurements, reducing scrap by 15%, dropped 1 test stage and improved diagnose-ability.
* Traced 2 recurring defects back to incoming material. Developed and documented incoming screening processes for backing dielectric breakdown and bulk capacitance reducing sensor scrap by 25%.
EDUCATION
BS, Applied Physics, University of Utah, Salt Lake City, UT
OTHER
Assistant Cub Scout Pack Leader, Southborough Pack 1
Assistant AA Little League Baseball Coach.
Math Volunteer Woodward Elementry
Marine Mammal rescue volunteer.