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Project Design

Location:
Benguluru, KA, India
Salary:
500000 per annum
Posted:
August 15, 2012

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Resume:

CURRICULUM VITAE

D.Rajesh,

S/o D.Satyanarayana, Email: dnr0r0@r.postjobfree.com

Dno: 2-82, dnr0r0@r.postjobfree.com

Durga Temple Street, Phone: +91-970*******

Savalyapuram,Vinukonda, +91-740*******

Guntur District, Andhra Pradesh.

CAREER OBJECTIVE:

To position myself in an enterprise where I shall get a chance to augment my technical skills and use them for the benefit of the society.

EXPERIENCE: Did Internship at Intel Technology India Private Ltd in Graphics DFX team for 8 months (Sep 2011 to May 2012).

ACADEMIC RECORD:

Class Board/University Year Percentage

M. Tech., VLSI Design. VIT University 2010-2012 7.3/10

B. Tech., EEE ANU 2004-2008 63.8

12th BIE - A.P. 2002-2004 87.2

10th SSC 2000-2002 77.7

TECHNICAL SKILLS:

• Programming Languages : Perl, UNIX commands, C, and C++.

• HDL Known : Verilog, System Verilog.

• Functional Verification Tool : Modelsim.

• Front end Tools : Design architect (Mentor Graphic’s), NC- sim (Cadence).

• Back end Tools : Soc Encounter (Cadence).

• Other Tools : Xilinx.

ACADEMIC PROJECT:

M.Tech:

TITLE: HVL AUTOMATED TEST ENVIRONMENT FOR VERIFICATION OF TAP CONTROLLER.

PROJECT DESCRIPTION:

Designed test environment to verify the functionality of TAP controller. Test bench designed using SystemVerilog.

TOOLS USED: VCS Simulator.

B.Tech:

TITLE: WAVELET BASED TRANSFORMER PROTECTION.

PROJECT DESCRIPTION:

In our project the main analysis is to” Distinguish between fault current and magnetizing inrush current”.

TOOLS USED: MATLAB SIMULATOR

MINI PROJECTS:

M.Tech:

TITLE: PERFORMANCE AND ENERGY CALCULATION OF FULL ADDER

PROJECT DESCRIPTION:

We have presented a less delay and lower power delay product circuit technique called transmission gate logic design based full adder.

TOOLS USED: DESIGN ARCHIET

TITLE: TEST PATTERN GENERATION WITH REDUCED SWITCHING ACTIVITY.

PROJECT DESCRIPTION:

This paper implements X-filling approach to reduce switching activity of the test patterns applied to CUT with scan based testing.

TOOLS USED: DFT ADVISOR, DEV C++.

PAPERS PRESENTED:

M.Tech:

• Presented a paper on “Performance and Energy Calculation of Full Adder” in International conference on Science, Engineering & Technology at VIT University.

• Presented a paper on “Test Pattern Generation with Reduced Switching Activity” in International conference on Science, Engineering & Technology at VIT University.

AREA OF INTEREST:

• ASIC

• VERILOG

• TESTING

• DIGITAL IC DESIGN

.

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge.

Date: (RAJESH DURISALA)



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