WILLIAM P. BOWMAN (Willy)

503-***-**** * dddm56@r.postjobfree.com

*** ** ***** ******, ********, Oregon 97225

SENIOR EXECUTIVE: Semiconductor Manufacturing Operations * Engineering *Supply Chain Management

Building and Leading World-Class Manufacturing Operations Teams, Flexible & Responsive Supply Chain Strategy and Partnerships, Continuous Improvement of product cost, quality and lead times.

Resourceful executive with a career-long record of innovation and results, leading operations and engineering within large and small multi-national corporations with rapidly changing and highly competitive environments.

Semiconductor product costing, margin analysis, supplier negotiations, cost reduction strategies and their implementation. Consistently delivered results which met or exceeded goals by coaching and working hands on with supply chain partners, direct reports and their staff to clearly understand the priorities and objectives.

Reputation as a tough but fair supply chain manager supported by partnerships that we can truly rely upon.

P&L responsibility at the operations level. Extensive and Valuable International supply chain network.

In depth background and experience in Semiconductor Product, Test, and Package Engineering (Including Copper wire development), as well as Quality and Reliability.

EXPERIENCE AND ACHIEVEMENTS

Lattice Semiconductor Corp.: Hillsboro, Oregon / *Singapore

$325M fabless semiconductor company that designs, develops and markets Programmable Logic Devices (PLDs) for a wide variety of consumer, industrial, automotive and military applications

Corporate Vice President – Manufacturing Ops & General Manager of Lattice SG Pte. Ltd. Jan ’10 – Aug ‘11

Oversee all manufacturing operations including Foundry, Product, Test and Package Engineering, Planning, Production Control, Shipping, Wafer Foundries and Subcontract Assembly & Test Partners with P&L responsibility at the Operations level. Drive operations for continuous improvement in COGS, cycle time, quality and customer delight.

Significant Accomplishments:

Led Japan crisis response team after March, 2011 disaster to successfully minimize impact of wafer and assembly supply chain issues on Q1 and Q2 customer deliveries.

Established a new Manufacturing Operations Site in Singapore in January of 2010 and transferred 90% of the product sustaining and cost reduction related responsibilities to the new team by Q3 2010.

Transitioned from Engineering to overall Manufacturing Operations management and led the team though one of our most rapid manufacturing ramps in history while still improving costs and margins and with no significant impact to customer on time delivery commitments.

Q409 Q110 Q210 Q310 Q410 Q111 Q211

Quarterly Sales ($M) 55.09 70.43 77.12 77.14 73.13 82.62 83.86

Mfg. Margin 55.4% 58.5% 61.2% 59.1% 62.8% 60.0% 60.4%

On Time Delivery 97.8% 98.1% 98.0% 98.0% 98.4% 98.3% 98.0%

Net Income ($M) 5.61 11.09 16.74 15.54 13.70 10.92 13.03

Instrumental in our successful turnaround and return to sustained profitability, implementing significant restructuring initiatives in Operations, establishing the new Singapore operations team, while continuing to stay focused on cost reduction and customer delivery priorities.

Successfully managed the Manufacturing Operations team from offshore (Singapore) for the first time in Lattice History.

Significantly improved supply chain partnerships with Foundries and Assembly Test suppliers through more straightforward negotiations and execution on all commitments, resulting in improved costs, quality and cycle time performance.

Refined supply chain price negotiations strategy by working closely with internal Business Units to clearly understand which areas we should focus on for maximum sales and margin impact.

Vice President – Manufacturing Engineering, Lattice Semiconductor (Continued) Aug ’06 – Dec ‘09

Oversee manufacturing engineering function including Product, Test and Package Engineering. Subcontract Assembly & Test Partnerships Strategy and Management. Drive Engineering and subcontractors for continuous improvement in Yields, Cycle Times, Test Time, Quality and Costs.

Significant Accomplishments:

Responsible for Subcontract Assembly & Test supplier strategy, selection, contracts and negotiations.

Led all engineering initiatives associated with supporting these partners

Led Yearly price negotiations with all Assembly / Test suppliers for average reduction of 7%/year.

Developed and deployed massively parallel wafer sort (40 site) and final test (8 site) on our high volume embedded FLASH CPLD products reducing test costs by more than 70%.

Led product and test engineering teams to successfully develop yield evaluation tools for 180, 130, 90, and 65nm products.

Tools have been instrumental in the rapid identification and elimination of yield limiting process defects in order to achieve world class defect density levels.

Led engineering effort in partnership with the Quality team to complete AEC-Q100 qualification of

4 product families for Automotive use and achieved TS-16949 certification for our facility

Key Manufacturing team member to drive implementation of the new Product Life cycle Management approach for new product development from feasibility through discontinuance.

Cost estimation of all proposed new products to help determine feasibility and for current products to establish product pricing targets .

Successfully developed and qualified ROHS compliant QFN’s, saw singulated LBGA’s (0.4, 0.5, 0.8 & 1.0mm ball pitch), Flip Chip BGA’s. Also qualified Copper wire LQFP and BGA packages.

Director – Manufacturing Engineering, Lattice Semiconductor (Continued) May ‘97 – Jul ‘06

Developed the product costing and margin analysis system; including all forward looking cost estimates for new and current products.

Cost reduction and all manufacturing margin improvements through sort, assembly and final test yield improvements, as well as test cost reduction and subcontractor pricing negotiations.

Manufacturing integration of acquired product lines:

Vantis CPLD and PAL product lines purchased from AMD in 1999.

Agere ORCA FPGA and FPSC product families acquired in January ‘02

Transferred all products to our preferred; sort, assembly and final test sites.

Converted test to more cost effective platforms and improved margins on these products from < 20% to > 60%.

Successfully doubled the size of the product, test, and assembly engineering groups and minimized the turnover in previously turbulent departments.

Led the corporate selection of all tester platforms used for all products in both development and production.

Successfully developed and qualified Power Quad QFP’s, Thermally Enhanced BGA’s, & PBGA’s (1.0 and 1.27mm pitch)

ST Microelectronics: Carrollton Texas / Phoenix, Arizona

Director of Engineering & Product Development, ST Microelectronics Sep ’93 – May ‘97

The PC-Micro division of ST Microelectronics was a $100M+/year x86 Microprocessor business.

Managed the successful start-up and qualification of wafer probe, final test and burn-in manufacturing areas for the new Phoenix facility.

Managed the timely process qualification of five new 0.6 and 0.55u HCMOS processes in four separate wafer fabrication facilities worldwide.

Overall Project Management responsibility (including 3rd party design company) for a new 0.25u 7th generation microprocessor.

Directly responsible for all product cost reduction through Yield Improvement and manufacturing cost reduction activities, effectively reducing costs for the 486 products by 60% in less than nine months.

Successfully managed the package development and qualification activities for all Ceramic and Plastic Pin Grid Arrays, Plastic QFP’s, Plastic Ball Grid Arrays and Flip Chip Packages.

Zilog Incorporated: Nampa, Idaho Feb ‘93 – Aug’ 93

Product / Test Engineering Manager, Front End Operations: Z8 Z80 and Z8000 microcontroller products

Effectively doubled the average wafer probe yields for all products in less than 7 months with the implementation of simple tools (dead zone analysis of stacked wafer maps) and procedures.

Led the reorganization of engineering group to better handle the split between yield improvement and general sustaining issues at wafer probe.

This included setting up a separate sustaining operation team, which operated during nights and weekends.

ST Microelectronics: Carrolton, Texas Dec ’87 – Jan ‘93

Engineering Manager, Semi-Custom Products, Programmable Products Group

Managed the timely process qualification of three new Standard Cell and Gate Array product families using double and triple metal, sub-micron processes.

Manufacturing margin improvement through test time and yield improvement.

Managed package development and qualification activities for Ceramic and Plastic PGA, PQFP, and PBGA Packages.

Developed and maintained all test capacity models and led next generation Tester platform selection team for our division.

VLSI Technology Incorporated: Tempe, Arizona / San Jose, California Jun ’84 – Nov ‘87

Senior Product Engineer, Government Products Group / Memory Products Group

Instrumental in the start-up of the Tempe, Arizona Government Products Engineering department and new test facility.

Evaluation of back-end (test and burn-in) equipment manufactures

Package development and qualification.

Documentation of all backend procedures.

Development of approximately 60 Military ASIC prototypes and release of 8 designs to MIL-STD-883 compliant production.

Developed 3 high density ROM’s, 2 Dual Port RAM’s and a high speed 64K EEPROM.

EDUCATION:

Bachelor of Science in Electrical Engineering (BSEE), 1984

Cornell University, Ithaca, New York

Six Sigma Lean Manufacturing, Product Life Cycle Management, Team Oriented Problem Solving, Statistical Methods for Improving Process Control (SPC), Project Management, Design of Experiments and Total Quality Management

LinkedIn Profile:

http://www.linkedin.com/pub/willy-bowman/0/6a1/103

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