Engineer Quality Control
Resume:
KIMLAN NGUYEN
Milpitas, CA *****
********@*****.***
OBJECTIVE: IC Mask Layout Designer
SUMMARY: Over 8 years of experience in the semiconductor industry.
• Fully Custom IC Layout design chip with 7 metal layers, from transistor form to tape out.
• Experience in building the macro cell unit and array.
• Completed mixed signals layouts, digital and analog layouts with FB, Comparator, Oscillator,
PLL, VCO, Charge pump… and I/O.
• LVS, DRC, ANT and ERC with Assura verification tool at blocks and chip level.
• Experience in Cadence Virtuoso Layout Editor, Virtuoso XL and Silicon Canvas layout tools.
• Performed floor-plan for the blocks and entire chip. Layout scheduling.
• Knowledge of UNIX, Linux, and Cadence Skill routines.
• Proficient with MS. Office such as Word, Excel, PP and Outlook.
SKILLS
• Knowledge of device matching principles such as common centroid layout, and critical signals.
• Able to squeeze the existing layouts to small spaces in transaction to new technologies.
• Strong communication skills in verbal and written reports in working distance.
• Hard working, fast learner, co-operative and responsible with minimum supervision.
Mask Layout Designer
Quick Logic corp., Sunny Vale, CA 01/ 2010 to 03/2010
Mask Layout Designer as a Consultant
• Modified the layout of block cells to updated schematics.
• Modified I/O cells, pad _ring.
• Completed LVS, DRC, and ANT verifications from block cells to top level, and the entire chip
for tape out.
Mask Layout Designer
Quick Logic corp., Sunny Vale, CA 12/ 2008 to 05/2009
Mask Layout Designer as a Consultant
• Completed custom layouts for a new project.
• Completed LVS, DRC, and ANT verifications from block cells to top level, and entire chip for tape out.
Mask Layout Designer
Quick Logic corp., Sunny Vale, CA 06/ 2000 to 10/2008
• Completed the custom layout from transistor level, block cells to top level in mixed signal IC with 7 metal layers process technology.
• Strong skills in floor plan for entire chip, assembly block cells, pad ring and manual routing.
• Performed Analog layout in mixed signal IC such as PLL, VCO’s, cpump, counter, Comparator, Regulator…
• Experience in Tanner’s L_Edit, Virtuoso Layout Editor, Virtuoso Layout XL and Silicon Canvas layout tools
• Experience with Assura for verification, debugging LVS, DRC and ANT from block cell to final chip Tapeout.
• Verified new DRC/LVS rule set in transition to new technology for designing or developing.
• Familiar to UNIX and Linux OS.
Mask Layout Designer
Micrel Semiconductor, Sanjose, CA 10/1999 to 06/2000
• Performed custom layout design in mixed signal IC and analog layout.
• Completed the custom layout sub-cells to block cells in dual metal layers of 0.18 um technology.
• Used Cadence virtuoso layout to layout the full custom layout of Transceiver, Differential AND/NAND, Multiplexer, Differential Flip-Flop, Quad Differential OR/NOR…
• Using Dracula and Diva to check DRC, LVS.
Manufacturing Technician
IBM CORP, San Jose, CA 1993 – 1998
• Responsible on testing RMA’s drives.
• Performed all the tasks of the Lab experiments before releasing those to production.
• Document the test yield for weekly meeting. Modifying the Eco’s for engineers with
Auto CAD 14 before releasing them to manufacturing.
• Supervised a manufacturing line of 10 people. Organized and structured all the works for workers in line.
• Trained and certified all operations in the process for new employees. Recorded weekly inventory in the department.
• Documented all SPCS (Sensitive Part Control System) in the department. Interface with engineer and PCN’s daily. Organized documents for coming ISO audit in the department.
Rework Analyzer
• Perform component level failure analysis for failed drives.
• Interpret failed test error codes through the rework channels via the reference manual.
Quality Control Inspector
• Performed final QA test for SCSI and ultra SCSI hard disk drives at packaging.
• Inspected visually and checked all the functional tests before shipping to customers.
EDUCATION & TRAINING
• A.S. Computer Electronic Technology, Mission College, Santa Clara.
• Industrial and Systems Engineering, San Jose State University, Santa Clara
• CMOS/BiCMOS IC Layout at Silicon Drafting Institute, Santa Clara.
• RFIC Layout Design at Silicon Valley Technical Institute, Santa Clara.
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