VLSI DESIGN

Address:#**, *** *****, **** ****,

Adarshanagar, Arisinakunte,

Nelmangala,

Bangalore-562123

Mobile: 996**-*****

Email:********@*****.***

OBJECTIVE: To build a challenging and interesting career where I can apply all of my skills & knowledge

for the upliftment of science & technology.

EDUCATIONAL DETAILS:

Currently Pursuing M. Tech in VLSI Design in NITK Surathkal (2009-2011) with the CGPA 7.44 upon 10 . Obtained Bachelor of Engineering (2005-2009) in Electronics & Communication Engineering with an aggregate of 84.84% . Completed PUC-II in PCMB with the percentage of 84.84 and SSLC with 88.48% .

TECHNICAL SKILLS:

Worked on MAGIC Tool for layout editing and Ngspice for circuit simulation.

Worked on Cadence tools and Xilinx ISE Simulator.

Programming in C, VHDL and Verilog.

Basics of Perl Scripting.

M.Tech Project:

Title : VERY HIGH SPEED SERIAL INTERFACE

Stream : VLSI DESIGN

Project details : In collaboration with HEIG-VD, Switzerland, the project involves development of the serial interface between two systems working at 20Gbps and above. Also, implementation of the communication between the boards of different vendors.

A brief on the other academic projects done:

Project No.1

Title : ROBO – RELAY

Stream :Robotics

Project details :Designing a pair of Robots which follow the given track and having baton exchange mechanism in them.

Project No.2

Title : FIRE – FIGHTER

Stream : Robotics

Project details : Designing a Robot which traverses the path guided by the walls, the walls were painted white in color. At the end of the track a candle will be there, the Robot need to turn off the candle.

Project No.3

Title : DESIGN AND IMPLEMENTATION OF VARIABLE LENGTH

ENCODER AND DECODER USING VERILOG HDL

Stream : Image Processing

Project details : To encode the pixel values of a given image and transmit to the destination. In the receiver side, the received data is decoded accordingly to obtain the original image. The encoding and decoding algorithms were implemented using Verilog HDL.

Project No.4

Title : DESIGN AND IMPLEMENTATION OF LOW POWER FIR FILTER

Stream : DSP & VLSI DESIGN

Project details : Design of the Low Power FIR Filter using Mat lab, VHDL. Layout is done with the SOC Encounter in Cadence.

ACHIEVEMENTS:

Participated in a Robo-Relay event held at IIT-KHARAGPUR

Won the first prize in the Fire-Fighter event conducted by RVCE

Secured First position in 6th Semester

Secured Second position in 4th Semester

Represented the college in a seminar on “FILTER DESIGNING”

at National Semiconductor, Bangalore

HOBBIES:

Solving SUDOKU

Reading magazines

PERSONAL PROFILE:

Name : Santosh K.M

Father’s Name : Mahadev K.N

Date of Birth : 14-07-1987

Languages Known : English, Kannada and Hindi

Permanent Address : #45,4th Block, 10th Main

Adarshanagar, Arishinakunte

Nelmangala, Bangalore - 562 123

Here by, I declare that the above written particulars and details are true to the best of my

knowledge and belief.

Place : Surathkal

Date : 15-02-2011

(SANTOSH K.M)

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