Senior Embedded Software Engineer

TONG WU **** Primrose Lane, Fox River Grove, IL **021

Tel: 847-***-****; Email: **********@*****.***

Objective: Senior Embedded Software Engineer Position

Specialty: Embedded Software Design/Development with Hardware Integration

• Programming Languages, Operating Systems /RTOS & Tools:

o C, C++, Object-oriented design/analysis (OOD/A), Design pattern, STL, UML, Perl, XML, BSD socket, Multi- threads, Concurrent programming, client/server architecture, Intel 8086 Assembly.

o Embedded Linux/UNIX, VxWorks, pSOS, multi-task communication and synchronization mechanism such as queue, event, signal, mailbox, semaphore and mutex; Windows NT/2000.

o UML, SDL, Rational ClearCase for software version control, MS Visual Studio.

• Microprocessor & Tools:

o IBM Power PC, PCI bus, PC104 architecture, Intel 8086, MC68K, FPGA, VHDL.

o Logic analyzer, Oscilloscope, HP Dynamic Signal Analyzer.

• Network Protocols and Wireless Communication:

o TCP/IP, SNMP, Ethernet, IPSec, TFTP, LAPD.

o TDMA, GSM, iDEN communication system.

Experience:

10/2006 – 12/2008 Senior Software Engineer Tellabs Inc, Naperville, Illinois.

Summary: Designed and implemented card provisioning, IPSec, Digital Certificate Network Security and control plan software components using C++, OOD/UML, STL on MS Visual Studio and VxWorks for 7100 Optical Transport Network Systems to provide voice, data and video services. The system supports both today and future native packet-based network services in a cost-effective and efficient manner. Participated in system releases.

• A “control plane” feature release. Developed special control center software for transmitting packet data through optical channels. Developed user command parser, data transmit and display functionality for different control plane components using C++ and STL on VxWorks. With the Control Plane, the packet-based data can be efficiently transmitted to its own destination without manually entering the path in the middle node. Thus, it improves the system flexibility and service delivery capacity.

• Designed and implemented software to replace 44 channels with 88 channels using C++ and STL on VxWorks, The release added OTNM multiplexer card, Elrame input amplifier card, ELrome output amplifier card to the Optical Transport system to replace 44 channels by 88 channels to double the transmit capacity..

• An Internet Protocol Security (IPSec) feature release. Understood IPsec, Public Keys, Private Keys, Digital Certificate, Internet Key Exchange (IKE), Security Association(SA), IKE Encryption and Authentication Algorithm, IPsec Encryption and Authentication algorithm. Participated in coding and testing using secure programming techniques. The release made the 7100 system work as a security network element in the Verizon network.

9/2000 – 9/2006 Senior Software Engineer Motorola Inc, Schaumburg, Illinois.

Summary: Understood wireless communication network iDEN system architecture. Knowledge of TDMA wireless communication system. Went through software life cycle and process to have designed, developed, implemented, tested and debugged variety of base radio Access Controller Gateway (ACG) software based on the requirements for iDEN enhanced base transceiver system using C on RTOS pSOS and Linux. Conducted official build and bundle for ACG software releases.

The ACG is responsible for controlling channel allocation for dispatch and telephone calls. It routes messages to Base Radios(BR), Base Site Controller(BSC), Transcoder(XCDR) and the Operations and Maintenance Center(OMC). It determines the channel quality of idle and busy channels, and does the handover if the call is switch to neighbor cell. It is multi-task, multi-threads software, about 60 tasks is concurrent running in pSOS environment, queues, events, signals and mailboxes are used for communication and synchronization among these tasks. It also uses TCP/IP, UDP, SNMP, TFTP, CMP, LAPD protocols.

Implemented performance functionality of CPU and memory usages of multiple Linux processes using C on Linux platform.

Participated in iDEN system Releases SR9.8, SR10.5, SR11.0 and SR13.0. Designed and updated different subsystems such as Radio Resource Telephone (RRT), Radio Resource Dispatch (RRD), Network Management (NM), Configuration Management (CM), State Management (SM), Performance management (PM), Alarm Management, Cell Resource Manager (CRM) etc.

• SR13.0: Designed and developed software for WiDEN handover project using C on pSOS. The release allowed iDEN system to handle WiDEN PCH handover and move interconnect call and dispatch call from PCH channel to Non PCH channel. It can optimize WiDEN resources and maximize WiDEN packet data capacity.

• SR11.0: Followed software requirement to change and add several new parameters to the ACG MIB. Designed and implemented On Line Change (OLCC) for these parameters and used SNMP protocol to download these parameters to base radio MIB with C.

• SR10.5: Designed and updated Radio Handover Subsystem (RHO) for Split 3 to 1 interconnect call. The RHO receives channel quality information from base Radios in the form of measurement reports, so ACG can select the best quality idle channel for each call.

• SR9.8: Designed and created a new task ACG_PEG which can log and report events within the ACG. The design allowed the events to be pegged with little processor overhead in the context of high priority tasks and ISRs. The events are collected on both a periodic and cumulative basis. The Peg Store contains the counts collected and can be accessed from the MMI and pROBE at any time.

1/1999 – 8/2000 Research Assistant

Department of Computer Science and Engineering

Wright State University, Dayton, Ohio

• Selected to have worked on a Defense Advanced Research Projects Agency (DARPA) project: was familiar with the architecture of FPGA supercomputing boards. Designed and developed resource manager multi-thread software to effectively utilize the FPGA board resources using C++ and MS Visual Studio on Windows NT. Each application thread uses sockets to create TCP reliable connection with main thread. Scheduler thread sends requests to loader thread. Loader thread loaded the imaging to FPGA board. Interrupt thread sent the results back to display. Utilized multi-threads to allocate memory and FPGA resources dynamically. Synchronized the multi-threads using signal and semaphore.

• Designed FIR and IIR DSP digital filter. Wrote the function of Linear Predictive Coders (LPC) to encode/decode a speech signal in MATLAB and C.

4/1995 – 9/1998 Software Engineer

The Research Institute of Navigation Technology, Xi'an, China

• Understood the architecture of GPS vehicle location report and data communication system. Developed the embedded software for the receiver to extract and display vehicle ID and position using Intel 8086 assembly and C on PC104 machine.

• Tested and debugged circuit board of a navigation receiver with logical analyzer and Oscilloscope.

• Developed analysis, test and control software for a HP dynamic signal analyzer in C.

• Developed interface, control and display software for a LED VISUAL Electronic Large Screen using C.

Technical Training: Motorola University, IL

o Digital Communication; Voice over IP (VoIP) ; Frame Relay

o CDMA2000 Implementation & Operational Issues: Understanding CDMA2000

o Wind River Systems PSOS Training Workshop

o Advanced C++ programming

o Specification And Description Language (SDL)

o Rational ClearCase

o Unix Shell Programming; Unix: Introduction; Perl Programming

o Six-sigma certificate; Formal Technical Reviews With Collaborative Team Skills

Education:

M.S. in Electrical Engineering (EE), Wright State University, Dayton, Ohio, 2000

M.S. in EE, Xidian University, Xi'an, China, 1995

B.S. in EE, Xidian University, Xi'an, China, 1990

References: Available upon request.

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