Design Project

CURRICULUM VITAE

PRAVIN KUMAR

V+P-Nauwachak, P.S-Patepur,

Via-Bariyarpur, Distt-Vaishali, Email: **********.***@*****.***

Bihar, India – 843102 Mobile: +91-990******* _______________________________________________________________________

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

Good Practice and knowledge about PIC MICROCONTROLLER(16F877A) both assembly & Embedded C language.

Designing and Manufacturing of Single Sided PCB.

VLSI Domain Skills

HDLs: Verilog

HVL: SystemVerilog and PSL

Verification Methodologies: Coverage Driven Verification Assertion Based Verification.

TB Methodology: :OVM,UVM,

EDA Tool: Modelsim,Questasim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore .

PCB Designing and manufacturing from ESTC(MSME) Uttrakhand .

PIC16F877A Microcontroller From ESTC(MSME) Uttarakhand.

Training Program of robotics, 8051 Embedded System & Automation from Kaizen Robonics, Jaipur.

Bachelor of Engineering, from Jagan Nath University, Jaipur, India Discipline:Electronics & Comm. Engineering Percentage: 73%. Year: June 2012

Achievements

Winner in Project competition (In university tech. fest competition,Two Times )

Presentation on “SMART DUST” in national level tech. fest.

Received the good performer award from Maven Silicon during the VLSI Design course.

Participate in Seminar of Western digital in Jaipur.

Experience

Maven Silicon, VLSI Design and Training Center, 4-month.

VLSI Projects

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description : The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

SPI Controller Core - Verification

HVL: SystemVerilog

EDA Tools: Modelsim, Questa -- Verification Platform

Description : The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock.This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register.The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

UART- IP Core – Verification

HVL : System Verilog

EDA Tools: Modelsim.

The UART IP core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various control and status registers. This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode. It is an interface between wishbone compatible UART transceiver, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. The UART core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Engineering Project

Microcontroller based message display using LED matrix & alphanumeric display (Final Yr. Major Project).

Project on “wireless fire fighting Robot(Final Yr. Mini project)

Areas of Interest

1. VLSI Design 2. Digital Electronics 3. Microprocessor & controller.

Programming Language Skills

1. Verilog. 2. SystemVerilog. 3.Embedded C & Assembly lang. 4. C/C++

Hobbies

Listening Music, Internet Browsing, Traveling

Personal Details

Name : Pravin Kumar

Date Of Birth : 03th Sept. 1990

Sex / Marital Status : Male / Unmarried

Nationality : Indian

Language known :Hindi, English

Permanent Address : S/O: chandeshwar ray, At +PO: nauwachak,

Via :bariyarpur, Distt: vaishali, Bihar - 843102.

Declaration: I hereby declare that all the information given about me is true to the best of my knowledge.

Date: 12-8-2012

Place: Bangalore (Pravin Kumar)

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