ASIC design/verification/testing

Danni Shi

*** ******** ***  Santa Cruz, CA *****  Phone: 317-***-****  Email: *****@****.**.***

Objective: ASIC design/verification/testing

- 3 years of experience in VLSI design and testing

-Familiar with digital IC design process, static timing analysis, pre-silicon simulation and silicon test

-Familiar with new technology on low power design, design for testability or DFT, design for reliability

-Technical skills include proficiency in VHDL, Verilog, Perl, C, C++ coding, Hspice, IRSIM, Magic, Synopsys VCS and Scirocco, familiarity with Modelsim, Synopsys Design Compiler.

-Good team work and always ready to learn new knowledge

Education

Master of Science in Electrical Engineering (in progress), University of Cincinnati, degree expected 08/2010, GPA 3.875/4.0

Bachelor of Science in Electrical Engineering, Beijing University of Technology, 7/2002, GPA 91/100

Research

Topic: Robustness Issues of Run-time Leakage Control in Nano-scale Technology (Matlab, Hspice, Perl)

-Develop an accurate circuit model for circuits under Reverse Body Bias (RBB) and Power Gating (PG) technologies considering inductance effect in 32nm technology.

-Quantitative analysis on the robustness issues of RBB and PG.

Course Projects

-ASIC Design: North-East Route Checker (VHDL, Hspice, Magic, IRSIM, HP Logic Analyzer 16550)

-The chip is designed by standard cells with CMOS 0.3 micron technology, fabricated using MOSIS SCMOS_SUBM technology.

-Follow the entire ASIC design flow from specification, behavioral and structural VHDL modeling and simulation, circuit verification and testing, DFT, static timing analysis, layout, and tape out.

-The design was optimized for area and throughput

-Perform post-silicon testing by designing a thorough test plan, which tests the stuck-at fault of every module and does functional testing for entire chip, reports maximum frequency of the chip.

- Low power design (Hspice, C++)

-Develop circuit model to estimate short circuit and dynamic power consumptions of electrical circuits with high accuracy.

-Cell library is designed and extracted by Hspice simulation.

-C++ program is used for logic simulation and to calculate the power consumption and delay.

- FPGA design (VHDL, Altera Quartus II, Altera FPGA cyclone)

Design and test a slot machine with mouse and monitor interfaces, and prototype onto Altera FPGA board.

- Design automation (C++)

-Develop a tool for circuit bi-partition by Simulated Annealing algorithm.

-Design circuit equivalence checker by disjoint SHARP operation.

- Analogue circuit design (Hspice, Magic)

-Design, layout and test an optical power meter, which includes transimpedance amplifier, non-inverting amplifier, unity gain buffer driver and 8-bit pipelined ADC.

-Design, layout and test an oscillator composed of Schmitt trigger.

- Digital circuit design (Hspice, Magic)

Design, layout and test a 4-bit ALU with bit-slice design and minimize area.

- Parallel computing (C, MPI)

Implement Data Encryption Standard (DES) algorithm by Message Passing Interface (MPI).

Coursework

Physical VLSI Design,

Low Power VLSI Design,

VLSI Test and Validation

VLSI Design Automation,

VLSI Multitech System,

Advanced Algorithms

Silicon Programming,

Operating System,

Advanced VLSI Low Power and Testing

Parallel and Distributed Computing,

Automata and Formal Languages

Experience

China Netcom-China, Beijing

Network Engineer, 8/2002 to 7/2006

Perform ADSL network maintenance including router, switch and server configuration and troubleshooting. Generate report of ADSL network in Beijing each month. Allocate resources for new applications.

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