Engineer Design

Jin-Fu Liou

****, ******** **** ******, *** Jose, CA,95132 ********@*****.*** Cell: 213-***-**** begin_of_the_skype_highlighting              213-***-****      end_of_the_skype_highlighting

Qualifications

． One year of industry experience for IC design and verification and two years experience in the system development of consumer electronic devices

． Can take a design from concept through to completion with strong trouble shooting ability.

． Experienced in behavior verification, module optimization and backend design and analysis.

Skills

． Programming/Modeling Languages: Proficient in Verilog, System Verilog, C and Matlab

． Familiar with Modelsim, Nanosim, NC-Sim, Composer-Schematic, Virtuoso (Layout), HSPICE

． CAD tools: Experience in Synopsys Design Compiler, SOCEncounter, Verplex, PrimeTime (STA)

． Others: Working knowledge of Microsoft office, including Word, Excel, Powerpoint, Visio

Professional Experience

Engineer, API Technology Inc, Santa Clara, California Aug. 2009 – Current

Supported the design and verification of CMOS ambient and proximity light sensor.

． Developed checking and driving tasks to validate and optimize Verilog modules.

． Successfully enhanced RTL modules to save 10% cell areas after synthesis.

． Experienced in coding the slave module of I2C bus using Verilog and developed test bench for

verification. Assisted in I2C communication timing analysis.

． Experienced with backend process, including synthesizing Verilog design using Synopsys Design

Compiler and performing static timing analysis and back- annotate simulation for digital circuits.

． Verified Verilog cell library against SPICE library and reported discrepancies.

． Analyzed full chip behavior and reported power consumption using Nanosim.

． Characterized products by testing and collecting data with Excel-macro scripts.

． Co-worked with design team and testing engineers to setup a measurement automation scheme to

speed up the debug process.

System Engineer, Sunext Technology Company Limited, Hsinchu, Taiwan Dec. 2003 –Apr. 2006

． Worked closely with ASIC and hardware design engineers to develop DVD-RW total solution

． Wrote C code to support both systems and validation efforts. Improved the servo control process including speed control process and seeking strategy and verified the signal quality on PC board with lab measurement equipment like Logic analyzer and Oscilloscope

． Supported read function, servo modeling and electro-mechanical integration.

． Developed the effective solutions for customers, analyzed the performance of products and gave valuable feedbacks to ASIC design team.

． Successfully completed the first mass production.

Project Experience

Digital Signal Process Lab - Real Time Sound Source Finder spring 2009

． Utilized the General Cross-Correlation algorithm to get correct time delay of arrival between microphone arrays and covert time delay into angle of sound source.

． Implemented the selected algorithm from Matlab simulation to C program. Successfully

implemented a real-time sound source tracking system with Texas Instrument DSK6713 DSP.

Troy Widen Word Processor fall 2008

． Used Veilog to realize a four-stage pipelined 32bits processor with a 32 depths x128 bits register.

． Capable of handling arithmetic, shift, logic instructions, with booth multiplication, hazard detection, forwarding, stall function and verified the post-synthesized net-list.

． Improved the operation speed by stall strategy for multi-cycle path and sharing logic on critical path to different stages to achieve top 10% in the speed competition.

Viterbi HIHO Decoder fall 2008

． Used Veilog to design an error detection decoder applied Viterbi HIHO algorithm with branch metrics, add-compare-select, and survivor path. Realized the algorithm from RTL to layout.

． Simulated the post- synthesized netlist with back- annotate timing information using NC-Sim and post-layout result with Nanosim.

． Wrote random data to simulate noisy channel and corrected data stream to evaluate performance.

Controller of Double Data Rate memory fall 2008

． Realized a finite state machine with Verilog to control the flow of initialization, refresh, read and write operation of Double Pulse rate memory and verified the result of the post-synthesized net-list (TSMC18).

． Solved the alignment problem of received data for data and address FIFO in sequential burst access.

Relevant Coursework

． Model a Finite State Machine for traffic light and vending machine with Verilog.

． Implement Digital Image Processing in C, including Enhancement, Noise Removal, Geometric Modification.

Education

M.S., Electrical Engineering,

University of Southern California, Los Angeles, California, Sept. 2007 - May 2009

M.S., Mechanical Engineering,

National Cheng Kung University, Tainan, Taiwan, Sept. 2001 - Jun. 2003

B.S., Mechanical Engineering,

National Cheng Kung University, Tainan, Taiwan,Sept. 1997 - Jun. 2001

Visa Status : F1-OPT and need future sponsorship for VISA

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