Engineer Quality Assurance
Resume:
RALPH GEIGER
Cary,NC *****
E-mail cdax1d@r.postjobfree.com
Skills
Programming/Tools: C++, C#, Assembly language, Visual Studio, SW compilers
and debuggers,
Verilog, VHDL, Cadence, MSOffice, MS Visio, Code Composer,Oscilloscope,
Logic analyzer Operating Systems:
Windows, DOS, AIX/UNIX, Linux, Real-time O/S and VM/CMS
Architectures: TI DSP,ARM, AVR, C51, PIC, Tensilica, Intel, PowerPC,
StrongARM, MIPS, and s/390
Professional Experience
DAC- Digital Audio Corp/Resolvit RTP,NC
March/2012-June/2012
World leader in forensic audio solutions
Senior Embedded Sw/Hw engineer
TI DSP's Analog/Digital Audio System Development
Embedded system development SW/HW
McASP MAC DMA DDR2 I2C I2S NAND USB Timers/WDT s/spdif OpAmp
tuning
JTAG Sys/Bios Code Composer PCB layout/debug
Test Fixtures design and development
Development and execution of test plans and test scripts.creation,
preparation, and conduct quality assurance
reviews. Analyzes, tests, and certifies application-specific
software and performs reviews
of business requirements and functional specification documents.
Logs, tracks, and
verifies resolution of software/hardware and specification defects
IBM/CTG Systems&Technology Group,RTP, NC
May/2010- June/2011
Contract engineering and technical project management positions.
CNA/VNA networking and storage
programs(pNIC/vNIC/iSCSI/FCoE /BOFM10Gb). Worked with local and
globe development teams/venders
supporting testing, resolving defects during bring up's and
DVT/SIT testing. ARM based ASIC's. ClearQuest
OneStopShop Notes Cogent(Tips/Deferrals)
Responsible for providing technical support regarding the
company's proprietary systems and software.
Assisted customers in troubleshooting hardware/software related
issues on various platforms.
Provided second/third level technical support for network
architecture (both hardware and software) to
customers, partners, account teams, and other engineers
consultation to independently troubleshoot & debug
product problems.
Applied analytical skills and technical knowledge to solve product
and network problems of moderate to high
complexity.
Provided technology/product training and intellectual property
material as required.
Effectively utilized moderate to complex lab setups to recreate
and solve problems.
Submitted complete and correct Defect reports in area of
expertise.
Acted as a technical expert and provides support on a world-wide
basis.
Interacted across technical assistance teams and development
teams at peer level.
All Headline News - IT Department West Palm Beach,FL
January-2009 Present
Systems Administrator- Linux/Windows based servers/pc's
AMM,IMM,UEFI,BIOS maintenance
Project lead - private cloud, VOIP
Porting hardware (IBM) and software (SUSE/Apache/SQL/Php)
Investigated technical problems to determine the root cause
Researched and answered customer questions, and provide other
front-end technical support activities
Researched and investigated client/product issues through analysis
of tickets and other information systems
Handled the most complex questions on functionality and product
usage, eliminating the need for Software
. Determined complex resolutions using existing product
technology and/or identify unique methods for
accomplishing tasks using multiple technologies
. Learned and mastered multiple Hosting and Managed Services'
offers across various environments to
provided quality customer support and to assist operational
and development staff
Sonavation-Application Engineering Palm Beach Gardens.FL
March-2008 October-2008
-Application development and implementation of microprocessor based
embedded systems and integrated circuits for digital and analog
applications used in fingerprint imaging for the biometrics market.
Software porting was targeted for cell phone hardware and O/S, such as
Symbian, WinCE and embedded Linux. PC porting for Linux, Windows XP and
Vista. Conducted research to establish design wins of Sonavation's
technology into product development over multiple disciplines with
technical demonstrations, representation, and instructions. Developed
hardware reference designs for the various solutions and integrated
Sonavation's software library into various host operating Systems and
hardware platforms. Provided technical feedback to the research and
development departments. Developed advance packaging solutions resulting in
increased reliability at a considerable cost reduction to Sonavation's
product line. Initiated a web based customer support service.
IBM Systems&Technology Group,RTP, NC 2006-2007
RSS & xSeries Server RAS Engineering
HW and FW development across Intel, AMD and VIA based
chipsets.
System verification and boot code development.
Reviewed and advised on all aspects of reliability, serviceability and
availability within the Retail Store Solution (RSS) division. The RSS group
designs and develops low end Kiosk units, Point of Sale (POS) PC's,
printers, USB Hubs and self check out systems.
Atmel Technical Resource, ARM Core based Microcontrollers, NC
2002-2006
-Director of USA/Canada application support for the ARM7/9 product family.
Provided technical sales, technical marketing and technical training to
corporate FAE's, and distributors FAE's. Developed SW projects for the
various evaluation boards, tool chains and OS's. Authored App Notes and
FAQ's to resolve key customer issues. Provided hands on customer support to
resolve any technical issues. Directed third party application issues until
a workable solution was provided. Coordinated failure analysis between the
customer and factory. Furnished technical support on ARM based ASIC's.
-FAE AVR based Microcontrollers
Software development for several key customers
TranSwitch Principal Member of Technical Staff, RTP, NC 1999-
2002
TranSwitch Corp. is a leading developer and global supplier of
semiconductor solutions that serve the Worldwide Public Network
Infrastructure, the Internet infrastructure and corporate Wide Area
Networks(WANS).
-Project Leader in the Advance Technology Center. The ATC's
charter was to set corporate directions which involved evaluating and
selecting external Intellectual Property(IP) or Procedures. Corporate
roll outs included a system on a chip(SOC) methodology, IP Reuse, OCP
system bus(SONIC) and reconfigurable processors.
Corporate transformations included switching from an internal MIPS
like processor to Tensilica's XTENSA processor and tool set. This
switch also led to adopting the ATI RTOS as a standard. Typical SOC's
contained multiple processors with customized OP's and as many as
twenty-four other IP blocks.
IBM Technical Lead on First PPCE Core, RTP, NC 1998-1999
-Developed, designed and verified the execution, instruction, data cache
and instruction cache units for a new superscaler embedded microprocessor.
The design, which will be incorporated into the ASIC library, will provide
SOC designers a high performance, high frequency, small die size, low power
and low cost solution to their design needs. An open architecture was
implemented to provide, depending on customer requirements, MAC, DSP, and
FP units. Developed and implemented a verification environment and tools
new to the PPCE test methodology. The objective was to reduce the
verification cycle while providing additional coverage based on previous
designs. This involved extensive cycle accurate C models and C based
stimulus generator. To cover specific code sequences an assembler type of
instruction set was developed.
IBM Technical Lead - Embedded Processor Performance, RTP, NC 1996-
1998
-Developed RTP's embedded benchmark suite. This suite specifically
targeted applications that covered the embedded processor market. The
embedded processor systems that were under study included the SA110, ARM7,
i960, MIPS 4300, MIPS 5000, SH3, PPC401, PPC403, PPC603, PPC740 and the
PPC750. Other factors that were taken into account while studying
performance involved several vender compilers, OS's, code density, power
requirements and debug environments.
IBM X86/PPC Processor Performance Engineer, Burlington, VT 1996-1996
-Developed Burlington's superscaler/superpipelined micro-processor
performance
verification methodology. Maximized processor performance by writing
analysis tools, which would identify software hot spots and hardware
bottlenecks. Carried out micro-architectural trade-off experiments,
analyzing results, and proposed solutions for optimal silicon
implementation. Pre/post silicon platforms were involved for both x86 and
PPC architectures.
CISC/RISC Microprocessor Development, Burlington, VT 1994-1996
-Responsible for the architectural/logic function verification of the
dispatch unit, memory management unit, and bus interface unit. Focus
covered both Uni/Multi-processor environments for a hybrid x86/PPC
processor. Developed the software drivers to emulate and irritate
interfaces, and the behaviorals to check for functionality, protocol, and
performance. The testbenches covered memory coherency, address
translation, exceptions, interrupts, snooping, load/store conflicts, store
forwarding, writeback, mispredicted branches, and self-modifying code. The
testbenches improved verification performance by targeting smaller models.
-Wrote a library of MASM testcases covering virtual, protected, and real
modes to verify Pentium compatibility.
IBM CMOS CISC Microprocessor Design, Poughkeepsie, NY 1992-1994
-Functional design verification team leader. Responsible for staffing and
establishing schedules for the verification of the hardware against its
logical model to meet project requirements. Designed and implemented a
Cache randomizer and logic simulator in C/C++ and PL/1. The code provided
a modeling framework for functional verification of designs. This included
tracking for all physical and logical model dependencies to ensure
completeness of test. Provided a hierarchical database to ensure that the
simulation and modeling stayed in sync while the design progressed.
IBM ES/9000 Mainframe Family, Poughkeepsie, NY 1987-1992
-Responsible for the overall design of the CPU Cache controller. Designed
ASICs and TCMs for the cache/buffer control element. Hardware timing,
ASTAP, and L/P checking coordinator. Coded simulation testcases using
PL1/REXX to cover all scenarios for a L1 Data Cache and L1 Instruction
Cache. Testing included out-of-order multiple pipeline execution, address
translation, cache set associativity, LRU management, delete bits, ECC, and
recovery to cover S/390 Architecture.
IBM Various Staff Engineering Positions, Poughkeepsie, NY 1978-1987
-Created processor models and researched benchmark findings, which
were used to define the optimal hardware implementation of the ES/9000
processor, based on a given technology. Provided subsystem and system
hardware bringup and clock stress testing. Wrote test cases and
assembler code test loops to functionally stress arrays and logic.
Performed critical path analysis using the APL Delay Calculator.
Education
B.S. Electrical Engineering 1978 GPA 3.5/4.0
Polytechnic University of New York
Special Honors ETA Kappa Nu
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