Engineer

Pankaj Chugh

*** * ******* ***** ***

Richardson, TX-75080

email: ***********@*******.***

Mobile: 916-***-**** , USA Green Card holder

________________________________________________________________

Objective To obtain the position that will enhance and broaden my current skill set and provide more challenging opportunities at work in technical positions.

Immigration status: Green card

Professional Experience

IBM, USA

Analog Circuit Designer

Design and layout of Operational amplifier (OPAMP), rail to rail input with Class AB output stage. 65nm 3.3v cmos10lp

Simulation and Layout of Resistive DAC for SAR ADC 65nm 3.3v cmos10hp

Design of Comparator for SAR ADC 65nm 3.3v cmos10hp

Design of level shifter for SAR ADC 65nm 3.3v cmos10hp

Solved many complex problems which helped me in improving my problem solving skills and analytical skills. Worked in a team and that helped me negotiate and improve my team building skills and communication skills.

Interacted with customers

Conexant, Hyderabad (India), August 2005 – Jan 2006

Senior Member Technical Staff- Project Lead and Project Management

Design of fully differential two stage OPAMP with CMFB for the subtractor in the hybrid. 1.8v 90nm

Study of Sigma Delta ADC

Matlab simulation of receiver in EPHY architecture

Regulator design 1.8v 3.3v 90nm

Feasibilty study of AFE for Gigabit PHY. Some of the blocks exposed to are:

Slope Controlled current steering DAC, Voltage and current mode hybrid, passive LPF, BLW, PGA, Pipeline ADC, subranging ADC, PLL, Bandgaps etc. I have managed 4+1 engineers for this project

Position of lead helped me improve my managerial,interpersonal, organizational and leadership skills. Learnt how to lead a team and balance team dynamics.

Interacted with vendors and customers

2002 - 2004 – Took Leave of Absence to attend family matters in India.

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Mixed Signal Design Engineer (Full-time) Advance Analog Products, Data Converters

• Texas Instruments, Dallas, Texas. Oct 1997 – July 2001

Projects

1) 12 bit 65MSPS Pipeline ADC, Design of Stages, Clock Generator, and Digital Correction, 0.35u CMOS, 3.3V

2) 14bit 70MSPS Pipeline ADC, Design of bandgap and current references , Voltage buffer, IO buffer RF BICMOS process, 3.3v

3) 10bit 100MSPS Integration of Two ADC on a single chip 0.18u CMOS process, 1.8V

4) 10 bit 240MSPS DAC Simulation of the Video DAC , Testing of a test DAC 0.18u CMOS, 3.3v

5) 14bit 70 MSPS with MNC. Simulation of ADC and auto-layout of MNC block RFBiCMOS, 3.3v

6) Autolayout (Place and route) of Several blocks in some of the projects above along with timing and Clock Distribution.

Comfortable with complete cycle of chip design and Project management. Have worked as a Team lead and individual contributor besides being a team member for some of the projects. Have held responsibility in various areas of design and other activities. Have taped out products.

Basic Building Blocks and other activities

1) Amplifiers (OPAMPS): Folded Cascode, Two stage CMOS, Telescopic,

single stage, Gain boosting, etc

2) References: Bandgap Reference, Voltage Buffer for Reference, etc

3) Auto layout (place and route) using Silicon Ensemble: Several blocks upto 20k gates

place and routed including clocks.

4) Buffers: Voltage Buffers

5) IO Buffers: IO buffers for high speed ADC

6) IO ring: IO ring design including selection of ESD and IO Buffers

along with ESD specialist

7) Pipeline Stages: Design of stages including top level simulation of

ADC

8) Stage Switches: Design and simulation of switches for pipeline ADC

9) Current references: Constant current and PTAT

10) Top level (System) simulation of ADC and DAC

11) Simulation and study of current cell DAC including design of

amplifiers for references.

12) Carried out extraction, verification and simulation and supervision

of layout , Floor-planning , Clock and Power Distribution

13) Study of different processes , Familiar with complete cycle of chip and detailed circuit design

14) Project Management, Conducting interviews for senior and junior analog positions , Led a team to study different types of packages

15) Carried out projects both as a team member and as a team leader

16) Selection of different circuit architectures for ADC and DAC , Debug and Characterization of test die received from Fab, Pin assignment,Noise Analysis

17) Basic and Advanced Courses in RF fundamentals.

18) Interacting with customers.

19) Comfortable with using lab equipment like meters, oscilloscope, analyzers etc.

Executive Instrumentation Engineer (Full-time) Oct 1992 – Dec 1994

• Deepak Fertilizers and Petrochemicals Corporation Ltd., Bombay, India.

Maintenance, Installation and calibration of various electronics, pneumatic, hydraulic instrumentation, valves and sensors in various chemical plants. Also, worked on DCS and PLC's. Have also supervised technicians.

Computer Skills

• Languages: C, Basic, FORTRAN , Pascal, Assembly (8086, DLXsim), HTML.

• Operating Systems: UNIX SUNOS5.5 (Solaris2.5), DOS 6.2, Linux and Windows.

• Simulators: Hspice, Pspice, Fiesta, Powermill, Switcap, Verilog and Cadence.

• Layout editor: Magic, Cadence,

• Databases: Oracle, Access Database.

• Others: Matlab, Word, Excel, Powerpoint, Trend distribution software and Maple, Hercules

Education

• M.S. Electrical Engineering, Texas A&M University,(TAMU) College Station, January 1995 - August 1997

Thesis: Switch Level Optimization for CMOS circuits

Advisor: Dr. Dhiraj Pradhan, Chair Professor at TAMU ( University of Bristol now)

I came up with a technique to reduce the number of transistors in Digital circuits at the switch level. This technique led to smaller size, lesser power dissipation and faster circuits. The techniques has been tested on several circuits like 4:1 Mux, Adder, Decoder etc. Two algorithms were also developed to implement the technique.

Papers : “A 14b 40 MSamples/s Pipelined ADC with DFCA” Published in ISSCC 2001.

Publishing paper in ICCAD/ DAC on a topic related to my thesis

• B.E. Instrumentation Engineering, University of Bombay, August 1988 - August 1992

Some of the Courses covered were Electronic design, Electronic Instrumentation, Process Control, Control Design, Transducers etc.

Course in Marketing at USD in 2008

Awards , Honors and extracurricular activities (past and present)

• Board Member of Indian diversity initiative at Texas Instruments

• Treasurer, IEEE Dallas Chapter for Circuits and Systems.

• Publicity Chair, IEEE workshop on Low Power circuits

• Member of IEEE.

Unix steering team member and External web development for data converters group at Texas Instruments.

• National Merit Scholarship for standing top 1% in HSC.

• Department Scholarship at Texas A&M University (Spring 1995).

.Award from President of India for an essay on Gandhi.

Arranged for blood drive at TI with carter blood care centre.

References

Available upon request

Contact this candidate