Engineer Design

STUART WOOTTEN

** ********* ****

Westbury-on-Trym

Bristol BS9 4AG

Tel: 0044 (0-117-***-****

Mobile: 0044 (0-791-*******

E-mail: ********@******.***

PROFILE

British, age 55

A successful electronics design engineer with wide experience of the Electronics industry for over 30 years, seeking contract positions. Excellent technical communication and inter-personal skills. Able to lead and motivate a team to produce quality results. Hard working and resourceful, able to work on own initiative or as part of a team. Seeking a challenging opportunity offering responsibility and reward.

CAREER HISTORY

1st October 2010 to 18th March 2011

ULTRA Electronics Command Control Systems

Engineering Department Product Support Group

Wimborne, Dorset

Product Support Engineer (Hardware)

The Product Support Group provides various obsolescence management services to the UECCS-Wimborne business including identification and tracking of obsolescent components and identification and justification of replacements. The Business has recently taken on a major obsolescence investigation project for a customer (Rolls-Royce Submarines) and requires additional resource to perform component investigation / substitution / justification and administration of the related documentation for both this project and to support the growing LTA manufacturing contract.

Hardware Component substitution and justification at military screening levels

General obsolescence engineering / production support for build and test

Component material investigations (RoHS) & non RoHS

Direct customer and supplier liaison

Safety case justifications/ reliability engineering

Hardware systems design and support including documentation.

May 2009 to June 2010

BAE Systems Inc: Rochester, Kent

HARDWARE DESIGN ENGINEER

Project 1

Redesign of IMDC

Integrated Mission Display Controller, Application Processor Module redesign, utilising

The Dual-Core Intel® Xeon® processor 3000 series, which combines the performance of

previous generation products with the power efficiencies of a low-power consumption which was a major consideration, microarchitecture to enable smaller, quieter systems on board military aircraft.

Another consideration was the complexity of the systems, the LAI is critical in providing the ability to probe and capture FSB signals & the complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive

heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system

level thermal solutions may consist of system fans combined with ducting and venting.

Perform: - Analogue and Digital design and development, throughout the product lifecycle,

Obsolescence issues, Root Cause Analysis, Component level test, debug and repair, Bill Of Material's.

Documentation for Test set design

Writing TRD document for Integrated Mission Display Controller 1 which was ITAR compliant to Mil standards 810F, RTCA DO160F, DO254 consisting of General Interface Module, Video Interface Module, Application Processor Module, Power supply Module. For the design of an ATE system to fault find down to component level on all modules. To be supplied to the KAI Korea Aerospace Industries – Republic of Korea Air Force program T50-TA50 Aircraft F-16 & VAAC Harrier.

November 2008 to March 2009

Diehl AEROSPACE GmbH, Uberlingen, Germany

SYSTEMS ENGINEER

Supplier Equipment Specification (SES) for A350XWB program, PTS, SES, DFS, Compliance Matrix documents analysis of equipment architecture and crosscheck with requirements and customer comments, Doors 8.3 for document control, definition of certification activities D0-254, D0178 related, analysis of derived requirements, Support reviews of the SES and SW documentation & preparation and support of open action responses to customer

May 2008 – October 31

GE VETCO LIMITED NAILSEA, BRISTOL

HARDWARE ENGINEER

Design & Development of Subsea Electronics module SEM 5

Involved in design & development of the SEM 5 & ATE. The design basis called for a common processing core to be used for the system on each ‘host module’ providing control, communications and data acquisition the Dual-Core Intel® Xeon® processor 5000 series was used. This structure enables each host module in the system to be “self sufficient”, managing their own power supplies and monitoring their own housekeeping with control and communications emanating from a central point (e.g. the modem host module).

The design basis called for the processing core to be implemented on a credit card sized Single Board Computer (SBC) mezzanine card, which will be located onto a carrier card prior to installation in the SEM. All appropriate processor interface signals and data buses shall be routed from the mezzanine card onto the carrier card to allow functionally specific circuitry to be located on the carrier board and to facilitate data communications between the SBC and the carrier card.

Tasks undertaken

Specification and design of micro-controller based date acquisition and control PCB assemblies

(PCBAs) SBC.

Design development and test of prototype electrical functions and assemblies.

Design of custom test equipment.

Generation and maintenance of general engineering design documentation.

Attendance of in house design reviews.

General engineering support for prototype equipments during Qualifications testing.

April 2006 – May 2008

AIRBUS UK Limited. Filton Bristol.

AIRBUS A320 A330 340 A350 LANDING GEAR AVIONICS ENGINEER.

Delivering control systems solutions primarily A350 programme as well as other Airbus aircraft variants A320 A340. Working in close cooperation with vendors, subcontractors & suppliers and design teams including attending regular design review meetings.

Conducting electrical circuit definitions defining avionics requirements both hardware & Integrating avionics systems, Control & indication interfaces within the cockpit.

Role: -

Implement and follow the Airbus processes and procedures for use within the A320 A330 A340 A350 A380 LGERS projects & Do 160 & Do245.

Configuration control, build standard and document control.

Writing system requirements in Doors.

Design of turnkey NI VME test system using LabView.

Hardware test & Qualification testing using Matlab & Simulink.

Redesign of Avionics Hardware for LGCIU Landing Gear Control Interface Unit,

IMA-Integrated Modular Avionics, LGCIS- Landing Gear Control Indication System,

CPIOM-Core Processing Input/Output Module, LGRDC-Landing Gear Remote Data Concentrator, AFDX-Avionics Full Duplex Switched Ethernet. Including Fault Monitoring & BITE.

V and V of the Avionics Equipment.

Liase with other Airbus systems concerning the avionics equipment installation and interfaces.

Documentation Using: -

Airbus people Portal, AirNAV AMM AWM ASM CMM TSM IPC, DOORS,

LGCIU Document Configuration Index

Perform: - Analogue and Digital design and development, throughout the product lifecycle,

Obsolescence issues, Root Cause Analysis, Component level test, debug and repair, Bill Of Material's.

October 2005 – March 2006

SMITHS AEROSPACE ELECTRONIC SYSTEMS Cheltenham.

HARDWARE ENGINEER.

Design & Development of 10 X 8 Large Area Display for Westland Helicopters Limited, Lockheed Martin & various other customers.

The IDU Integrated Display Unit consist of a AMLCD 2108 Display Head assembly, ARINC 600 connector connected to a filter card connected to a Back plane with slots for seven cards.

The seven cards fitted are Filter card, I/O card, GFX card (Graphics), APPS card, AVT (Analogue Video) card, DVT (Digital Video).

Hardware is Free Scale MPC85XX Power PC for the I/O & APPS cards & Altera FPGA Stratix EP1S25

Hardware is ATI Radion M9 processor for the graphics card & Altera FPGA Stratix EP1S25

The IDU Utilises Rapid Buses, ARINC 708 & 429, RS 422, Ethernet.

Test system used was NI VME Base & LabView.

Documentation Using:-

Doors Databases & PSMS.

Writing the following procedures TRD Test Requirements Document, ATP Acceptance Test Procedure, ESS Environmental Stress Screening, IDU Signal name database (Doors).

EH101 Helicopter manufactured by Westland Helicopters Limited

The CDS system cockpit display system is for the EH101-based aircraft, the cockpit layout will contain 5 IDUs. There will be two crew stations associated with the cockpit displays, for the Pilot and Co-pilot/Observer. Two IDUs will normally be associated with each crew station, one normally presenting Primary Flight information and the other normally providing Secondary Navigation information. The additional IDU (IDU#3) sits in the centre and normally shows Systems Management Information (relating to engines, fuel et). All displays are configurable to show different data when selected.

Each unit will be identical in terms of software and hardware and will determine its cockpit position, and thus required operation, from ident pins.

Perform: - Analogue and Digital design and development, throughout the product lifecycle,

Obsolescence issues, Root Cause Analysis, Component level test, debug and repair, Bill Of Material's.

April 2004 – October 2005

DSTL Porton , Salisbury Wilt.

ELECTRONICS DESIGN ENGINEER.

Design & Development of electronic equipment, provide electronic support to MOD & other customers.

Current Projects

1/ Design sonar system ATE for fault detection down to component level of control system pcb’s for type 45 destroyer.

2/ Design ESAS 40K Volts 4K AC HV detection system using NI VME hardware & labView for control system

3/ Design Hardware, Build & test five pre-production NPT GOLDS for DOH Chlamydia field trial & project management of all technical areas.

Hardware is Hitachi H8 & Altera FPGA based for 5x station control PCB & 1 x supervisor

PCB. PCB’s have embedded software downloaded to both the H8 & the FPA. Initial test software is LabView 6i vi’s based. Station PCB controls 3 x Maxon motors & 3 x air valves,

2 x pressure sensors, 1 x thermopile PCB, & various switches & solenoids.

Supervisor PCB is H8 & FPA based & controls 5x station PCB’s by 5 x serial ports.

September 2003-April 2004

MULTIPULSE Ltd Woking .

ELECTRONICS TEST SYSTEMS DESIGN ENGINEER .

TRAIN SWITCH UNIT DESIGN

Writing full design specifications for TSU, TRAIN SWITCH UNIT audio/analogue design specifications Design & build five prototypes for client Motorola for London underground.

The TSU was to be sited in the drivers cab & controls all Train communications. Full project lifecycle & Design Of all PCB’s.

TEST SYSTEMS DESIGN

Writing Test specifications for the test system for testing the above units & future units which were National Instruments based using LABview 6i software for automated testing.

May 2001-April 2003

TAYLOR ASSOCIATES. BRISTOL. BLUESKY TECHNOLOGY Plymouth.

ELECTRONICS DESIGN TEST ENGINEER

Developing turnkey ATE & test solutions for telecomms & electronic applications, principally in optical & wireless access test technology for clients Nortel, Marconi, JDS, NI & LABview VME & LABview CVI Teststand.

October 2000-May 2001

BOOKHAM TECHNOLOGY LTD, OXFORD

ELECTRONICS-OPTICAL DESIGN TEST ENGINEER

Designing Reliability test systems for the following DWDM ASOC products for central office & transmission stations OCM Optical Channel Monitor, 40 channel AWG, Arrayed Waveguide Gratings,40 channel VMUX Variable Optical attenuator Wavelength multiplexer for Lucent Technologies & Alcatel.

Test systems are National Instrument's VME or Exfo based using LabView software reliablity tests covered were Mechanical Integrity, Monitored Endurance tests for 5000 hours. The VMUX product mother board required additional verification, all parts were certified, the Hitachi H8 processor HD64334CP16 was selected due to the advantage of in circuit programing of its flash memory, support circuitry for flash download was included on the PCB.

Download is accomplished via the serial port using the Hitachi HMSE flash download module & PC application. Control of the module is through the monitor programme which comprises a single window, once started the programme attempts to establish a link to the hardware via COM1 or COM2 Also PCB design.

October 1998-October 2000

RADIODETECTION LTD, BRISTOL

ANALOGUE-DIGITAL DESIGN TEST ENGINEER

Designing test systems for LMS-3 Product for AT&T for detection of fibre optic cables, which consisted of comms card, I/O cards, Processor card Used a Intel 8086 processor 16bit.PACID Module. Hardware design using EPLD,CPLD,FPGA XILNX XC4000E/X Up to XC4010E/X were used to implement the above board design's, then migrated to hardwired mask-programmed devices. The Foundation Express system used advanced synthesis technology from Synopsys .

Perform: - Analogue and Digital design and development, throughout the product lifecycle,

Obsolescence issues, Root Cause Analysis, Component level test, debug and repair, Bill Of Material's.

May 1996-September 1998

LSI LOGIC EUROPE LTD, BRACKNELL.

ASIC ANALOGUE-DIGITAL DESIGN TEST ENGINEER

PROJECT 1

Design, Simulation & Analysis of test chip LQA0015 using Synopsys, Cadance, schematic capture, tools in G11 G12 family. Hyper-LVDS high speed I/O Performing well beyond 1 Gigabit per second to support SONET/SDH Standards PCML Buffers at 622MHZ 1.2GHZ for telecommunications applications. The chip was of mixed signal, digital logic and VCO, PLL, CPU

The CPU was a Motorola 68060 32 bit 50MHz,using Machine code. SIPO, PISO 64 bit S/R SER/PAR load, Divide by 8,Sync divider, ASYNC divider, Clock recovery units, data aligners. Cell design complete, the chip was fabricated at LSI Logic in California and was tested at wafer level; Some Wafer & packaged chips were shipped to the UK for device level transistor probing & Characterization. The chips were then used to populate test boards for demonstration to customers Alcatel Telecommunications and 3COM.also PCB design

PROJECT 2

Design simulation & analysis of test chip AD-DA0250 8 MEG Flash Ram Analogue to Digital & Digital to Analogue converters using the above tools at resolutions up to 10-bit and conversion frequencies exceeding 250 MHz , Sigma Delta converters provided additional resolution to as many as 16-bits for the BBC. The chips are intended for Digital Video Applications.

PROJECT 3

Design simulation & analysis of test chips for next generation Cisco 12000 series gigabit switch router GSR for large IP networks using the above tools. The router series will ensure that Internet and intranet will continue to scale upward under the weight of the ever burgeoning traffic volumes. The seven chips, ranging in performance from 100 – 125 MHZ provide the core logic using the latest packaging technology E-PBGA. Running simulations & analysis to determine if cell design and layout changes will improved performance. This having been done 4 sets of chips were fabricated and shipped to the UK for probing & Characterization. also PCB design.

Laboratory Test Equipment for Testing .

HP7000 MMS System

HP70841B Pattern Generator

HP70842B Error Detector

Hp70004A Controller

HP70820A MTA Microwave Transition Analyser

Tektronix HFS9003 Stimulus System

Tektronix CSA 907A Pattern Generator

Tektronix CSA 907A Error Detector

Tektronix CSA 803A Communications Signal Analyser

November 1995-to April 1996

LUCAS AUTOMOTIVE PLC CIRENCESTER .

ELECTRONICS DESIGN & TEST ENGINEER

PROJECT 1

Involved in design & development of Common rail ECU, Miss Fire detection, Knock detection, Adaptive cruise control, Continuously variable transmission. Hardware testing / developing modern automotive hardware control systems. Also designed stand alone and production test equipment for ECU's, Electronic Control Units, for automotive systems for BMW, FORD, PEUGEOT car Manufacturers.

Using Visio for circuit design prototyping and wire scheduling component sourcing, mechanical front panel layout. This design documentation was then used by a technician to build a prototype stand alone system. Having verified correct operation of the prototype, PCB's were designed using mentor-graphics for production of a further units .

PROJECT 2

To design production test equipment for testing ECU's, the system was design using the HP75000 VXI modular system, incorporating HP70207A

The processor card for the above ATE systems used a Cyrix x86 32bit 100MHz processor chip. also PCB design.

October 1994-November 1995

LIEBERT PLC, SWINDON.

ELECTRONICS DESIGN & TEST ENGINEER

PROJECT 1

Product comparisons, Testing Liebert and competitors 'UPS's against clamed performance. Assimilate and compile documentation on test results.

PROJECT 2

As a result of the above tests the following design considerations were looked at:-

Power reserve capacity for future growth of the facility .

Inverter current surge capability, is the system driving inductive loads.

Output voltage & frequency stability over time & with varying loads.

Required battery supply voltage & current. Battery costs vary greatly.

Type of UPS system forward or reverse transfer type dependent on usage .

Inverter efficiency at typical load levels, some Inverters have good efficiency at 90% loads but poor efficiency at light loads.

Size & environmental requirements of the UPS system high power UPS equipment requires a large amount of space for the inverter & control equipment & batteries.

September 1993-October 1994

HILTON NATIONAL, WATFORD .

IT SUPPORT ENGINEER

Key responsibilities - Call logging, Helpdesk support of Ethernet network running Novell V4.00, various MS packages, Lotus Notes, CC Mail.

August 1992 to September 1993

LSI LOGIC EUROPE LTD, BRACKNELL.

ELECTRONICS DESIGN & TEST ENGINEER

Design and develop test set up and write documentation to demonstrate LSI 500 1 Gigabit Transputer to the press and customers IBM, DEC. also PCB design

1991 to 1992

RADIODETECTION LTD, BRISTOL.

ELECTRONICS TEST ENGINEER

Designing hardware on sonar system locators for AT & T for uses on underground utilities. Hardware change implementation and PCB redesign.

1990 to 1991

3COM Ltd HEMEL HEMPSTEAD .

DEVELOPMENT TEST ENGINEER

Testing alarm manager part of the network management System transend enterprise manager for windows. Testing of alpha test specification for Ethernet and token ring networks and smart agent software for network management. Full performance testing. Utilising : snmp and fddi devices, Distinct TCP/IP V3.1, Chameleon NFS V4.00, telnet, ping utilities, 3COM Boot server V2.00, TFTP V2.00, VT 100 isoview, isolan test units tardis 1181, smartbit multiport analyser, ET100 Etherwindows VX 2.1. Capture & analysis OOD.

1989 to 1990

LMT SYSTEMS LTD, MIDSOMMER NORTON.

RADIOCOMMS RF DESIGN ENGINEER

Full System design & test of base stations, Mobiles, combiners, Sub-assembly test receivers, power amps, Tcc , SCI, for US & European markets, Marconi 2032 HP 8657A,HP89038 audio analyser, INRIT MS2601b Spectrum analyser.

1987 TO 1989

SCIMED LTD, BRISTOL.

SENIOR R & D DESIGN ENGINEER

Involved in the design & manufacture of digital Doppler ultrasound measuring equipment for blood flow analysis. Digital FPGA ASIC design ALTERA, XILNX, Integrated FFT Frequency ANALYSIS, digital,

Analogue, RF design, Microprocessors, Micro controllers, GSP, DSP, EPLD, FPGA, SMT, EMC, ISO 9000.

1986 to 1987

THE EXTEL GROUP PLC , CLEVEDON.

PRINCIPAL FIELD SERVICE ENGINEER

Responsible for six field service engineers supporting PC's, Novell, NT, Networks.

1979-1986

UNIVERSITY of the WEST of ENGLAND. BRISTOL.

ELECTRONICS TECHNICIAN

Design & development of lab equipment, also test & calibration.

HARDWARE:

Most bespoke 386, 486, 586, Pentium 133, 266 PC's Networking: Novell, Paxus, Unix, Xenix, 3Com. Interfaces CAN, TCP/IP, Ethernet, VME, GPIB, PPP, Profibus, Modbus.

SOFTWARE:

Ms dos, Windows, Windows 95, Windows NT, Unix, Xenix, Novell Netware, Sun Solaris, Ms Office, Lotus Notes, Framemaker, Lattice, CAE Altera Maxplus II, Synopsis, Cadance, Mentor Graphics, Viewlogic, LabView 6i & Teststand, AutoCad 5.00, Isodraw 4.00 PCMS, Doors V7.

QUALIFICATIONS:

2003 BRUNEL COLLEGE

Certificate in ELECTRICIAL INSTALLATIONS BS7671

16th Edition, IEE regulations.

1975-1980 UNIVERSITY OF THE WEST OF ENGLAND, Bristol

HND in Electronic Engineering . B.Eng (Hons) Electronic Engineering

1972-1975 BRUNEL COLLEGE

London Institute of Electronics City & Guilds

Electronics for technicians passed with distinctions

1967-1972 CLARKS GRAMMER SCHOOL, Bristol.

2 GCE 'A’ levels - 7 GCE 'O' levels

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