M.Tech FRESHER in VLSI System Design

KATTEKOLA NARESH

M.TECH VLSI SYSTEM DESIGN (****-2010)

Mobile: +91-964******* E-mail: ****************@*****.***

OBJECTIVE

Seeking a technical position in IT or VLSI field that will allow me to challenge my skills, assume responsibilities and professional growth while being resourceful, innovative, and flexible.

PROFESSIONAL EXPOSURE

Extensively developed distributed design applications using technologies Xilinx.

Good knowledge in Cadence Tools, Verilog & VHDL Languages.

Good knowledge on Manual Testing, Good exposure to Software development life cycle (SDLC) and Software testing life cycle (STLC).

Quick learning, Good communication skills.

Good team player with excellent technical and inter personnel skills.

ACADEMIC QUALIFICATION

M.Tech in VLSI System Design (66.21%) from J .N .T University, 2008-2010.

B.Tech in Electronics & Communication Engineering (66. 17%) from J .N .T University, 2003-2007.

Intermediate (82.9%) from Board of Intermediate Education in 2000-2002.

S.S.C (76.6%) from Board of Secondary Education in 2000.

TECHNICAL EXPERTISE

Software Languages : C

Scripting Languages : PERL

HDL Languages : Verilog & VHDL.

Tools : Simulator: NC Sim, Synthesizer: RTL Compiler, SOC

Encounter & Virtuoso, Xilinx ISE.

Analog Tools : CADENCE ICFB.

Operating Systems : Windows XP/2000/VISTA, LINUX, MS-DOS.

Testing Tools : Manual Testing

PROJECT SUMMARY

Project 1:

Title : Implementation of Digital Clock.

HDL : Verilog.

Tools : Xilinx ISE.

Description:

The digital clock is implemented using Structural Verilog HDL program on the Spartran 3 FPGA board. This clock is having minutes and hours set operations. The 4 segment displays in the board are used for display either minutes and hours or seconds and minutes with a selection input. It is implemented and verified on Spartran 3 FPGA Board using Xilinx ISE software.

Project 2:

Title : Scrolling Message.

HDL : Verilog

Tools : Xilinx ISE.

Description:

Scrolling message is implemented using structural Verilog HDL program on the SPARTAN3 FPGA board. This module is having a 26 bit counter which converts the 50 MHz system clock present in SPARTAN3 board to a 1Hz signal. Rom module is used to store the seven segment code for each character of the message. The data through the Rom is accessed with a frequency of 1Hz and the same is displayed on the seven segment display of SPARTAN3 board.

ACADEMIC PROJECT (M.TECH)

Title : ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.

Tools : Cadence Tools (ICFB, NC Sim, &Virtuoso).

Description:

The ROM-Based Logic Low-Power 16x16 multiplier is to be designed. The ROM-Based Logic design uses sixteen 4x4 ROM-based multiplier blocks followed by carry-save adders and a final carry-select adder to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance.

The design of a low power multiplier is thus the goal of my thesis work. The design is in the 180nm technology to end up with fully chip level layout by achieving high speed of operation based on Cadence ICFB environment tools. The Schematics, Layouts, LVS and parasitic extraction are done through Cadence Virtuoso. The verification of results is through Cadence Spectre simulator along with power analysis in each part of the design.

ACADEMIC PROJECT (B.TECH)

Title: Electro Dermal Activity Meter.

Description:

The aim of the project is to measure the person's skin conductance. The mental state of the person is varying with the skin conductance of that person. By using the skin conductance value we can estimate the mental response of the human body. The different states of the human body are Excited, Arousal, Relaxed, and Normal. The design includes push buttons, LCD display, 'Al” electrodes, and mega 32. This Electro Dermal Activity Meter used in traditional lie detectors and also used in psychology fields.

PERSONAL PROFILE

Date of Birth : 12th May, 1985

Father Name : Sri. K.Narsaiah

Languages known : English, Hindi and Telugu

Strength : Hard and smart working, Self motivate, grasping

Things quickly and can work with team efficiently.

Address : H.No: 8-3-228/690/2, Rahmath nagar, Yousuf guda,

Hyderabad, 500045

[K.NARESH]

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