Design Engineer

MANINDER PAL SINGH

**** ****** ******** **** • Centreville • VA - 20120 • ******************@*****.*** • 703-***-****

EDUCATION

Masters of Science in Electrical Engineering (GPA-3.27) Jan’2011

Post Graduation Diploma in Embedded Systems and VLSI Design Jan’2008

Bachelors of Technology in Electronics and Communication May’2007

PROFESSIONAL EXPERIENCE

Teaching Assistant at George Mason University Aug’09 – Dec’10

• Instructed MATLAB scripting for Introductory DSP course.

• Taught Bread Board Design and PCB layout design for Digital Electronics Class.

Hardware Engineer Intern at PUNCOM Ltd Jan’06 – Jul’06

• Studied ARM -7 TDMI Processor Architecture.

• Developed API using C++ for serial to parallel conversion of bit stream data using ARM7-TDMI kit.

Digital Design Intern at STEP IIT-Roorkee Jun’05 – Jul’05

• VHDL coding and CPU Design concepts.

• Implemented 32-bit MIPS Microprocessor on SPARTAN FPGA.

ACADEMIC PROJECTS

Design of Array and Sequential Multipliers

• N - Bit Generic Array and Sequential Multiplier architecture design using VHDL.

• Radix - 4 Booth Recoding with Carry Save Adder was used to make a faster Sequential Multiplier.

• Minimum Latency times Area optimization was achieved and Verified against MATLAB implementation.

Keywords: VHDL, MATLAB, RTL, Generic Design, Design Verification, Perl, Synplify pro, Test Bench.

Datapath and Controller design for Luffa Hash Function

• Algorithm was realized by writing Pseudo - code from specifications and the reference C implementation.

• Datapath Architecture was developed and optimized for maximum throughput to area ratio.

• ASM was developed to design the Controller.

• Designed multiple architectures (folded and unrolled) Optimized for minimum latency - area product for maximum use of embedded FPGA resources.

• The design was coded using VHDL and was verified against given test vectors and corresponding outputs.

Keywords: Computer Arithmetic, Pipelining, FPGA (Xilinx/Altera), RTL, Computer Architecture, FSM, ASM, C.

Two Stage Operational Amplifier Design

• A two stage Operational Amplifier was designed according to the given specifications.

• Parameters: μNCOX = 110 μA/V2, μPCOX = 50 μA/V2, VTN/P = +/-0.5 V, λN = 0.05 V-1, λP = 0.2 V-1, L = 0.2 μm

Keywords: Orcad – PSPICE, 0.2 μm Channel length (L), ICMR, Slew Rate, Semiconductors.

ASIC Level Synthesis of SHA-1 Design using 90nm technology

• Static timing analysis of SHA – 1 Design written in VHDL was performed using Design Compiler.

• Formal Verification was done using Formality tool

• Floor Planning, Placement and Routing were done using Astro.

Keywords: Synopsys - Design Compiler/Primetime/Formality/Astro, Tcl, Linux, STA, DFT, SoC, ASIC design.

Design and optimization of Clock Driver

• Balanced the Clock network by inserting buffer stages between the source and final loads.

• Ensured that Clock network induces minimum Skew.

• Overall energy dissipation of the buffers was minimized using Spice simulations.

Keywords: Microwind 2.6, PSPICE, 0.25 μm CMOS Process, Semiconductors, Layout Design, DRC.

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