Engineer Customer Service

JAVIER SAENZ

*** *. ******* *** ****, AZ ***** • 512-***-**** • ******.******@*****.***

SENIOR FAILURE ANALYSIS ENGINEER

Yield Enhancement Engineering Reliability Engineering

Combine astute, multi-disciplined high technology experience with a 15 year track record of successful performance in parametric/functional fault isolation, physical failure analysis using conventional and advanced analytical techniques, CMOS manufacturing processes, circuit analysis, and surface analysis. Highly developed interpersonal communication skills and organization skills. Wide knowledge of IC semiconductor packaging, quality and failure analysis disciplines.

AREAS OF EXPERTISE

Scanning Electron Microscopy Mechanical polishing Light Emission Microscopy

Focus Ion Beam Cross-sectioning Identifying Failure Mechanisms

Scanning Auger Microprobe OBIRCH Microscopy ATE (Automated Test Equipment)

Package-level FA Layouts Customer Service

UNIX-Camelot/Cadence Micro-Probing Bench Testing

PROFESSIONAL SUMMARY

MICROCHIP TECHNOLOGY INC.

The leader in high-performance 8-bit, 16-bit, and 32-bit microcontrollers

Senior Failure Analysis Engineer Chandler, AZ 2006 to Present

Determined root-causes on Micro-controllers for chronic process induced defect mechanisms and putting permanent solutions in place for package-level and wafer-level silicon.

Evaluate customer returns and reliability failures with ATE data logs, memory programmers, pattern tools, assembly language programming, layout investigations, and mentor junior engineers.

FREESCALE SEMICONDUCTOR

The leader in high-performance 8-bit, 16-bit, 32-bit microcontroller Austin, TX 1999-2006

Senior Failure Analysis Engineer

Served as failure analysis coordinator to all nation-wide failure analysis laboratories to manage database and communicate top defectivity issues to management.

Principal investigator for yield loss, excursion lots, SRAM bit-map failure analysis, in-line defectivity investigations, and electrical bench analysis on low yielding lots.

Most significant technical contributor on “Spacer Etch Optimization” and improved the 90nm HCMOS7 technology yield by 20% (2005).

STMICROELECTRONICS

High performance semiconductors Carrollton, TX 1992 - 1999

Reliability Engineer

Led implementation of WLR including reliability evaluation, testing, and assessment.

Evaluation of HCI, Qbd, Vbd, TDDB, transistor characteristics, autoclave, temp-cycle, electromigration, constructional analysis, and thermal bias stressing (TBS).

Key member during tool qualifications, technology transfers, and assessing lab submissions.

TEXAS INSTRUMENTS

High performance semiconductors Dallas TX, 1986-1992

Engineering Technician

Performed electrical characterization on transistors, diodes, capacitors, and resistors.

Supervised Multi-probe operators on test program loading, probe card evaluations, and correlation evaluations.

EDUCATION & PROFESSIONAL DEVELOPMENT

A.S. – Electronics Texas State Technical College, Harlingen TX

HONORS & AWARDS

Technical Excellence Award – Freescale Semiconductor Inc. Austin, TX

Bravo Award -- Freescale Semiconductor Inc. Austin, TX

Trade Secret NO.1056 – ST Microelectronics, Phoenix, AZ

TECHNICAL PUBLICATIONS

“AS-Deposited Properties and Rapid Thermal Annealing Effects on Ti/TiN Barrier Layer for AL Plug Technology (1994-V-MIC).

“Practical Application of wafer level Reliability Control Program” (1994 Microelectronics Manufacturing Symposium).

REFERENCES

Principal Engineers: Guang Bo Gao Phd. 951-***-****, Surinder Hunjan 480-***-****

Senior Engineers: Mike Richey 480-***-****, Fred Nassif 512-***-****

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